XIO2221 datasheet(3/196 Pages) TI1

3 / 196 page

XIO2221

www.ti.com

SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

4.8

Header Type Register

.................................................................................................... 50

4.9

BIST Register

.............................................................................................................. 50

4.10

Device Control Base Address Register

................................................................................. 50

4.11

Scratchpad RAM Base Address

......................................................................................... 51

4.12

Primary Bus Number Register

........................................................................................... 51

4.13

Secondary Bus Number Register

....................................................................................... 51

4.14

Subordinate Bus Number Register

...................................................................................... 52

4.15

Secondary Latency Timer Register

..................................................................................... 52

4.16

I/O Base Register

.......................................................................................................... 52

4.17

I/O Limit Register

.......................................................................................................... 53

4.18

Secondary Status Register

............................................................................................... 54

4.19

Memory Base Register

................................................................................................... 55

4.20

Memory Limit Register

.................................................................................................... 55

4.21

Prefetchable Memory Base Register

................................................................................... 56

4.22

Prefetchable Memory Limit Register

.................................................................................... 56

4.23

Prefetchable Base Upper 32 Bits Register

............................................................................. 57

4.24

Prefetchable Limit Upper 32 Bits Register

............................................................................. 57

4.25

I/O Base Upper 16 Bits Register

........................................................................................ 58

4.26

I/O Limit Upper 16 Bits Register

......................................................................................... 58

4.27

Capabilities Pointer Register

............................................................................................. 59

4.28

Interrupt Line Register

.................................................................................................... 59

4.29

Interrupt Pin Register

..................................................................................................... 59

4.30

Bridge Control Register

................................................................................................... 60

4.31

PM Capability ID Register

................................................................................................ 62

4.32

Next Item Pointer Register

............................................................................................... 62

4.33

Power Management Capabilities Register

............................................................................. 63

4.34

Power Management Control/Status Register

.......................................................................... 64

4.35

Power Management Bridge Support Extension Register

............................................................ 65

4.36

Power Management Data Register

..................................................................................... 65

4.37

MSI Capability ID Register

............................................................................................... 65

4.38

Next Item Pointer Register

............................................................................................... 66

4.39

MSI Message Control Register

.......................................................................................... 66

4.40

MSI Message Lower Address Register

................................................................................. 67

4.41

MSI Message Upper Address Register

................................................................................. 67

4.42

MSI Message Data Register

............................................................................................. 68

4.43

SSID/SSVID Capability ID Register

..................................................................................... 68

4.44

Next Item Pointer Register

............................................................................................... 68

4.45

Subsystem Vendor ID Register

.......................................................................................... 69

4.46

Subsystem ID Register

................................................................................................... 69

4.47

PCI Express Capability ID Register

..................................................................................... 69

4.48

Next Item Pointer Register

............................................................................................... 69

4.49

PCI Express Capabilities Register

...................................................................................... 70

4.50

Device Capabilities Register

............................................................................................. 71

4.51

Device Control Register

.................................................................................................. 72

4.52

Device Status Register

................................................................................................... 73

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