(

)

(

)

( )

m

×

=

Tss ms Iss

A

C6(nF)

Vref V

×

-

REF

OUT

REF

R7 V

R8 =

V

V

(

)

(

)

(

)

Voutmin

Ontimemin Fsmax Vinmax

Ioutmin RDS2min

RDS1min

Ioutmin RL

RDS2min

=

×

+

-

-

+

TPS54821

www.ti.com

SLVSB14

– OCTOBER 2011

Slow Start Capacitor Selection

The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its

nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This

is also used if the output capacitance is very large and would require large amounts of current to quickly charge

the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the

TPS54821 reach the current limit or excessive current draw from the input power supply may cause the input

voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft start capacitor

value can be calculated using Equation 28. For the example circuit, the soft start time is not too critical since the

output capacitor value is 2 x 47

μF which does not require much current to charge to 3.3 V. The example circuit

has the soft start time set to an arbitrary value of 6 ms which requires a 22 nF capacitor. In TPS54821, Iss is 2.3

uA and Vref is 0.6V.

(28)

Bootstrap Capacitor Selection

A 0.1

µF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is

recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10V or

higher voltage rating.

Under Voltage Lockout Set Point

The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R3 and R4.

R3 is connected between VIN and the EN pin of the TPS54821 and R4 is connected between EN and GND .

The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or

brown outs when the input voltage is falling. For the example design, the supply should turn on and start

switching once the input voltage increases above 6.528V (UVLO start or enable). After the regulator starts

switching, it should continue to do so until the input voltage falls below 6.190 V (UVLO stop or disable).

Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the

stop voltages specified the nearest standard resistor value for R3 is 35.7 k

Ω and for R4 is 8.06 kΩ.

Output Voltage Feedback Resistor Selection

The resistor divider network R7 and R8 is used to set the output voltage. For the example design, 10 k

Ω was

selected for R7. Using Equation 29, R8 is calculated as 2.22 k

Ω. The nearest standard 1% resistor is 2.21 kΩ.

(29)

Minimum Output Voltage

Due to the internal design of the TPS54821, there is a minimum output voltage limit for any given input voltage.

The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V, the output

voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by

Equation 30

Where:

Voutmin = minimum achievable output voltage

Ontimemin = minimum controllable on-time (135 nsec maximum)

Fsmax = maximum switching frequency including tolerance

Vinmax = maximum input voltage

Ioutmin = minimum load current

RDS1min = minimum high side MOSFET on resistance (36-32 m

Ω typical)

RDS2min = minimum low side MOSFET on resistance (19 m

Ω typical)

RL = series resistance of output inductor

(30)

Copyright

© 2011, Texas Instruments Incorporated

Submit Documentation Feedback

23

Product Folder Link(s) :TPS54821