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DESCRIPTION

PCI4510R GVF/ZVF

SLLA239 – JUNE 2006

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Register Bits Give Software Control of

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PCI Power-Management D0, D1, D2, and D3

Contender Bit, Power Class Bits, Link Active

Power States

Control Bit, and IEEE Std 1394a-2000

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Initial Bandwidth Available and Initial

Features

Channels Available Registers

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Isochronous Receive Dual-Buffer Mode

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PME Support per 1394 Open Host Controller

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Out-Of-Order Pipelining for Asynchronous

Interface Specification

Transmit Requests

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Advanced Submicron, Low-Power CMOS

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Register Access Fail Interrupt When the PHY

Technology

SCLK Is Not Active

The Texas Instruments PCI4510R device is an integrated single-socket PC Card controller with an IEEE 1394

open host controller link-layer controller (LLC) and two-port 1394 PHY. This high performance integrated

solution provides the latest in both PC Card and IEEE 1394 technology.

The controller is compliant with PCI Local Bus Specification. Function 0 provides the independent PC Card

socket controller compliant with the latest PC Card Standards. The controller provides features that make it the

best choice for bridging between the PCI bus and PC Cards, and supports either 16-bit or CardBus PC Cards in

the socket, powered at 5 V or 3.3 V, as required.

There are no PCMCIA card and socket service software changes required to move systems from the existing

CardBus socket controller to the PCI4510R controller. The PCI4510R controller is register compatible with the

Intel 82365SL–DF ExCA controller and implements the host interface defined in the PC Card Standard. The

internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for

maximum performance. Independent buffering and the pipeline architecture provides an unsurpassed

performance level with sustained bursting. The controller can be programmed to accept posted writes to improve

bus utilization. All card signals are internally buffered to allow hot insertion and removal without external

buffering.

Function 1 of the controller is an integrated IEEE 1394a-2000 open host controller interface (OHCI)

PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus

Power Management Interface Specification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open

Host Controller Interface Specification. It is capable of transferring data between the 33-MHz PCI bus and the

1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The controller provides two 1394 ports that have

separate cable bias (TPBIAS). The controller also supports the IEEE Std 1394a-2000 power-down features for

battery-operated applications and arbitration enhancements.

As required by the 1394 Open Host Controller Interface Specification and IEEE Std 1394a-2000, internal control

registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through

configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the

controller is compliant with the PCI Bus Power Management Interface Specification as specified by the PC 2001

Design Guide requirements. The controller supports the D0, D1, D2, and D3 power states.

The controller provides PCI bus master bursting, and it is capable of transferring a cacheline of data at 132M

bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided

to buffer the IEEE 1394 data.

The controller provides physical write posting buffers and a highly-tuned physical data path for SBP-2

performance. The controller also provides multiple isochronous contexts, multiple cacheline burst transfers,

advanced internal arbitration, and bus-holding buffers.

The PHY-layer provides the digital and analog transceiver functions needed to implement a two-port node in a

cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers

include circuitry to monitor the line conditions as needed for determining connection status, for initialization and

arbitration, and for packet reception and transmission.

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