TNETX15VE datasheet(74/113 Pages) TI1

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TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

EEPROM initialization/automatic loading (LOAD)

The TNETX15VE automatically loads selected registers from an attached 24C02 EEPROM after a hardware

reset or when the LOAD bit in the control register is set. Up to eight 24C02 EEPROMs can be connected across

the same serial interface. They are distinguished by separate addresses that are selectable by pulling address

terminals up or down on each EEPROM. The TNETX15VE requires the automatic loading information in device

number 0x00, starting at location 0x00.

The TNETX15VE determines if the EEPROM device is present. Several conditions cause the TNETX15VE to

determine that a device is not present. If EDIO is pulled down, the EEPROM is assumed to be not present. If

the EEPROM fails to acknowledge (Ack) on data writes, the EEPROM is not present. If the cyclic redundancy

check (CRC) in the EEPROM does not match the internally calculated CRC, the EEPROM is determined to be

not present.

When no EEPROM is detected, The TNETX15VE sets the NEEPM bit in the control register to a 1, and

TNETX15VE is placed in a reset state (RESET and NEEPM are set in the control register) while the registers

assume their default values.

The organization of the EEPROM data is roughly equivalent to the TNETX15VE registers 0x01–0x05 and

0x50–0xEF. The automatic loader reads the register values from the EEPROM and programs the TNETX15VE

accordingly. The last register written is the control register.

The automatic loader can initialize and start up the TNETX15VE if the START bit in the control register is

programmed in the EEPROM. This allows for initialization and startup without a host CPU.

During the automatic loading, no DIO operations are permitted. Both reads and writes stall, that is, SRDY does

not come true on a pending operation until the EEPROM load cycle is over. The load cycle should take (bits per

word) * (words read) * 100 kHz, or 27 * 162 * 100 kHz, or 44 ms. To sense the end, wait for a sample register

read to complete, or wait 50 ms. The download bit, LOAD bit, RESET bit, and any other read only or reserved

bits cannot be set during automatic loading. The CRC for the EEPROM is calculated using the information

written in the EEPROM although information may not be written to the TNETX15VE. For example; a value of

0x8F or 0xFF in the EEPROM for RAMsize are both written as 0x0F in the TNETX15VE since bits 7, 6, 5, and

4 are reserved, but the calculated CRC for the EEPROM for each case is different. As another example, the

byte at 0x2E is currently reserved. The value in the EEPROM is not used, but it is included in the CRC

calculation.

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