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TMS570LS3134 датащи(PDF) 73 Page - Texas Instruments

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номер детали TMS570LS3134
подробное описание детали  TMS570LSxxx4 16/32-Bit RISC Flash Microcontroller
PDF  155 Pages
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TMS570LS3134 датащи(HTML) 73 Page - Texas Instruments

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TMS570LS3134
TMS570LS2134
TMS570LS2124
www.ti.com
SPNS165
– SEPTEMBER 2011
4.9.3
Master/Slave Access Privileges
The table below lists the access permissions for each bus master on the device. A bus master is a module
that can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed
in the "MASTERS" column can access that slave module.
Table 4-22. Master / Slave Access Matrix
MASTERS
ACCESS MODE
SLAVES ON MAIN SCR
Flash Module
Non-CPU
CRC
EMIF, Ethernet,
Peripheral
Bus2 Interface:
Accesses to
Slave Interfaces
Control
OTP, ECC,
Program Flash
Registers, All
EEPROM Bank
and CPU Data
Peripheral
RAM
Memories, And
All System
Module Control
Registers And
Memories
CPU READ
User/Privilege
Yes
Yes
Yes
Yes
Yes
CPU WRITE
User/Privilege
No
Yes
Yes
Yes
Yes
DMA
User
Yes
Yes
Yes
Yes
Yes
POM
User
Yes
Yes
Yes
Yes
Yes
DMM
User
Yes
Yes
Yes
Yes
Yes
DAP
Privilege
Yes
Yes
Yes
Yes
Yes
HTU1
Privilege
No
Yes
Yes
Yes
Yes
HTU2
Privilege
No
Yes
Yes
Yes
Yes
EMAC
User
No
Yes
No
Yes
No
4.9.3.1
Special Notes on Accesses to Certain Slaves
Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU
(master id = 1). The other masters can only read from these registers.
A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.
The device contains dedicated logic to generate a bus error response on any access to a module that is in
a power domain that has been turned OFF.
Copyright
© 2011, Texas Instruments Incorporated
System Information and Electrical Specifications
73
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focus.ti.com: TMS570LS3134 TMS570LS2134 TMS570LS2124



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