SM320DM6446 datasheet(3/228 Pages) TI1

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1.3 Description

SM320DM6446

Digital Media System-on-Chip

www.ti.com

SPRS607A – JUNE 2009 – REVISED JUNE 2009

The TMS320DM6446 devices (also referenced as DM6446 and including the SM320DM6446) leverages

TI’s DaVinci™ technology to meet the networked media encode and decode application processing needs

of next-generation embedded devices.

The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating

systems support, rich user interfaces, high processing performance, and long battery life through the

maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set

Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an

ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and

processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and

memory system can operate continuously.

The ARM core incorporates:

• A coprocessor 15 (CP15) and protection module

• Data and program Memory Management Units (MMUs) with table look-aside buffers.

• Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual

index virtual tag (VIVT).

The

TMS320C64x+™

DSPs

are

the

highest-performance

fixed-point

DSP

generation

the

TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation

high-performance,

advanced

very-long-instruction-word

(VLIW)

architecture

developed

Texas

Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a

code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of

the C64x+™ DSP with added functionality and an expanded instruction set.

Any reference to the C64x™ DSP or C64x™ CPU also applies, unless otherwise noted, to the C64x+™

DSP and C64x+™ CPU, respectively.

With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the

C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses

the operational flexibility of high-speed controllers and the numerical capability of array processors. The

C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly

independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The

eight functional units include instructions to accelerate the performance in video and imaging applications.

The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million

MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details

on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide

(literature number SPRU732).

The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip

peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level

cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the

Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2)

consists of an 512K-bit memory space that is shared between program and data space. L2 memory can

be configured as mapped memory, cache, or combinations of the two.

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Digital Media System-on-Chip (DMSoC)

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