RM48L930 datasheet(49/147 Pages) TI1

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3.3 V

CCIOPORH

1.2 V

CCPORH

CCIOPORL

(1.2 V)

/ V

(3.3 V)

CCIO

CCP

nPORRST

CCPORL

IL(PORRST)

/ V

CCIO

CCP

CCPORL

IL(PORRST)

CCIOPORH

CCPORH

CCIOPORL

NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing.

RM48L930

RM48L730

RM48L530

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SPNS176

– SEPTEMBER 2011

4.3.2

Power-Down Sequence

The different supplies to the device can be powered down in any order.

4.3.3

Power-On Reset: nPORRST

This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core

supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an

internal pulldown.

4.3.3.1

nPORRST Electrical and Timing Requirements

Table 4-4. Electrical Requirements for nPORRST

NO Parameter

MIN

MAX

Unit

VCCPORL

VCC low supply level when nPORRST must be active during

0.5

power-up

VCCPORH

VCC high supply level when nPORRST must remain active during

1.14

power-up and become active during power down

VCCIOPORL

VCCIO / VCCP low supply level when nPORRST must be active during

1.1

power-up

VCCIOPORH

VCCIO / VCCP high supply level when nPORRST must remain active

3.0

during power-up and become active during power down

VIL(PORRST)

Low-level input voltage of nPORRST VCCIO > 2.5V

0.2 * VCCIO

Low-level input voltage of nPORRST VCCIO < 2.5V

0.5

tsu(PORRST)

Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL

during power-up

th(PORRST)

Hold time, nPORRST active after VCC > VCCPORH

tsu(PORRST)

Setup time, nPORRST active before VCC < VCCPORH during power

µs

down

th(PORRST)

Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH

th(PORRST)

Hold time, nPORRST active after VCC < VCCPORL

tf(nPORRST)

500

2000

Filter time nPORRST pin;

pulses less than MIN will be filtered out, pulses greater than MAX

will generate a reset.

Figure 4-1. nPORRST Timing Diagram

System Information and Electrical Specifications

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