SN8P1602A datasheet(49/76 Pages) SONIX

49 / 76 page

SN8P1602B

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 49

Version 1.1

8 TIMERS

WATCHDOG TIMER (WDT)

The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into

the unknown status by noise interference, WDT overflow signal raises and resets MCU. The instruction that clears the

watchdog timer (“ B0BSET

FWDRST “) should be executed within a certain period. If an instruction that clears the

watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and

system is restarted.

0CAH

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCM

WTCKS

WDRST

CPUM1

CPUM0

CLKMD

STPHX

Read/Write

R/W

After reset

WDRST: Watchdog timer reset bit. 0 = Non reset, 1 = clear the watchdog timer counter.

WTCKS: Watchdog clock source select bit 0 = Fcpu, 1 = internal RC low clock.

Watchdog timer overflow table.

WTCKS

CLKMD

Code Option

Watchdog Timer Overflow Time

4M_X’tal / 12M_X’tal / RC

1 / ( Fcpu

÷ 214 ÷ 16 ) = 293 ms, Fosc=3.58MHz

32K_X’tal

1 / ( Fcpu

÷ 28 ÷ 16 ) = 500 ms, Fosc=32768Hz

1 / ( Fcpu

÷ 214 ÷ 16 ) = 65.5s, Fosc=16KHz@3V

1 / ( 16K

÷ 512 ÷ 16 ) ~ 0.5s @3V

Enable Int_16K_RC

1 / ( 16K

÷ 512 ÷ 16 ) ~ 0.5s @3V

Note: The watchdog timer can be enabled or disabled by the code option. If disabled, the watchdog

timer can also be served as fixed-period timer by checking the NT0 flag.

Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top

of the main routine of the program.

Main:

B0BSET

FWDRST

; Clear the watchdog timer counter.

CALL

SUB1

CALL

SUB2

JMP

MAIN

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