HCT373 datasheet(4/5 Pages) SLS

номер детали	HCT373

подробное описание детали	Octal 3-State Noninverting Transparent Latch(High-Performance Silicon-Gate CMOS)

PDF	5 Pages

Scroll/Zoom	100%

производитель	SLS [System Logic Semiconductor]

домашняя страница	http://www.slsemicon.co.kr/e_index.htm

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4 / 5 page

SL74HCT373

System Logic

Semiconductor

SLS

AC ELECTRICAL CHARACTERISTICS(V

CC =5.0 V

± 10%, C

L=50pF,Input t r=tf=6.0 ns)

Guaranteed Limit

Symbol

Parameter

°C to

-55

°C

≤85°C

≤125°C

Unit

tPLH, tPHL

Maximum Propagation Delay, Input D to Q

(Figures 1 and 5)

tPLH, tPHL

Maximum Propagation Delay , Latch Enable to Q

(Figures 2 and 5)

tPLZ, tPHZ

Maximum Propagation Delay ,Output Enable to Q

(Figures 3 and 6)

tPZL, tPZH

Maximum Propagation Delay , Output Enable to Q

(Figures 3 and 6)

tTLH, tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

CIN

Maximum Input Capacitance

COUT

Maximum Three-State Output Capacitance

(Output in High-Impedance State)

Power Dissipation Capacitance (Per Latch)

Typical @25

°C,V

CC=5.0 V

CPD

Used to determine the no-load dynamic power

consumption:

PD=CPDVCC

2f+I

CCVCC

TIMING REQUIREMENTS (V

CC =5.0 V

± 10%, C

L=50pF,Input t r=tf=6.0 ns)

Guaranteed Limit

Symbol

Parameter

°C to

-55

°C

≤85°C

≤125°C

Unit

tSU

Minimum Setup Time, Input D

to Latch Enable

(Figure 4)

Minimum Hold Time,Latch

Enable to Input D

(Figure 4)

Minimum Pulse Width, Latch

Enable (Figure 2)

tr, tf

Maximum Input Rise and Fall

Times (Figure 1)

500

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