SL74HCT273 datasheet(4/5 Pages) SLS

номер детали	SL74HCT273

подробное описание детали	Octal D Flip-Flop with Common Clock and Reset(High-Performance Silicon-Gate CMOS)

PDF	5 Pages

Scroll/Zoom	100%

производитель	SLS [System Logic Semiconductor]

домашняя страница	http://www.slsemicon.co.kr/e_index.htm

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4 / 5 page

SL74HCT273

System Logic

Semiconductor

SLS

AC ELECTRICAL CHARACTERISTICS(V

CC =5.0 V

± 10%, C

L=50pF,Input t r=tf=6.0 ns)

Guaranteed Limit

Symbol

Parameter

°C to

-55

°C

≤85°C

≤125°C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

MHz

tPLH, tPHL

Maximum Propagation Delay, Clock to Q (Figures

1 and 4)

tPHL

Maximum Propagation Delay , Reset to Q (Figures

2 and 4)

tTLH, tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

CIN

Maximum Input Capacitance

Power Dis sipation Capacitance (Per Gate)

Typical @25

°C,V

CC=5.0 V

CPD

Used to determine the no-load dynamic power

consumption:

PD=CPDVCC

2f+I

CCVCC

TIMING REQUIREMENTS (V

CC =5.0 V

± 10%, C

L=50pF,Input t r=tf=6.0 ns)

Guaranteed Limit

Symbol

Parameter

°C to

-55

°C

≤85°C

≤125°C

Unit

tSU

Minimum Setup Time, Data to

Clock (Figure 3)

Minimum Hold Time, Clock to

Data (Figure 3)

3.0

trec

Minimum Recovery Time,

Reset Inactive to Clock (Figure

5.0

Minimum Pulse Width, Clock

(Figure 1)

Minimum Pulse Width, Reset

(Figure 2)

tr, tf

Maximum Input Rise and Fall

Times (Figure 1)

500

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