LTC4271 datasheet(14/32 Pages) LINER

14 / 32 page

LTC4290/LTC4271

429071f

PIN FUNCTIONS

LTC4290

VEE (Pins 1, 30, 33, 40): Main PoE Supply Input. Con-

nect to a –45V to –57V supply, relative to AGND. Voltage

depends on PSE type (Type 1 or Type 2).

GATEn (Pins 2, 4, 7, 9, 22, 24, 27, 29): Port n Gate Drive.

GATEn should be connected to the gate of the external

MOSFET for port n. When the MOSFET is turned on, the

gate voltage is driven to 12V (typ) above VEE. During a

current limit condition, the voltage at GATEn will be re-

duced to maintain constant current through the external

MOSFET. If the fault timer expires, GATEn is pulled down,

turning the MOSFET off and recording a port fault event.

If the port is unused, float the GATEn pin.

OUTn (Pins 3, 5, 8, 10, 21, 23, 26, 28): Port n Output

Voltage Monitor. OUTn should be connected to the output

port. A current limit foldback circuit limits the power dis-

sipation in the external MOSFET by reducing the current

limit threshold when the drain-to-source voltage exceeds

10V. The port n Power Good bit is set when the voltage

from OUTn to VEE drops below 2.4V (typ). A 500k resistor

is connected internally from OUTn to AGND when the port

is idle. If the port is unused, the OUTn pin must be floated.

CAP2 (Pin 6): Analog Internal 4.3V Power Supply Bypass

Capacitor. Connect 0.1µF ceramic cap to VEE.

XIO0(Pin11):GeneralPurposeDigitalInputOutput.Logic

signal between VEE and VEE + 4.3V. Internal pull up.

SENSEn (Pins 12, 13, 14, 15, 16, 17, 18, 19): Port n

Current Sense Input. SENSEn monitors the external MOS-

FET current via a 0.5Ω or 0.25Ω sense resistor between

SENSEn and VEE. Whenever the voltage across the sense

resistorexceedstheovercurrentdetectionthresholdVCUT,

the current limit fault timer counts up. If the voltage across

thesenseresistorreachesthecurrentlimitthresholdVLIM,

the GATEn pin voltage is lowered to maintain constant cur-

rent in the external MOSFET. See Applications Information

for further details. If the port is unused, the SENSEn pin

must be tied to VEE.

XIO1(Pin20):GeneralPurposeDigitalInputOutput.Logic

signal between VEE and VEE + 4.3V. Internal pull up.

AGND (Pin 25): Analog Ground. Connect AGND to the

return for the VEE supply.

DNA (Pin 36): Data Transceiver Negative Input Output

(Analog). Connect to DND through a data transformer.

DPA (Pin 37): Data Transceiver Positive Input Output

(Analog). Connect to DPD through a data transformer.

CNA (Pin 38): Clock Transceiver Negative Input Output

(Analog). Connect to CND through a data transformer.

CPA (Pin 39): Clock Transceiver Positive Input Output

(Analog). Connect to CPD through a data transformer.

VSSK (Exposed Pad Pin 41): Kelvin Sense to VEE.Connect

to sense resistor common node. Do not connect directly

to VEE plane. See Layout Guide.

Common Pins

NC, DNC (LTC4271 Pins 7,13; LTC4290 Pins 31, 32, 34,

35): All pins identified with “NC” or “DNC” must be left

unconnected.

LTC4271

AD0(Pin1):AddressBit0.Tietheaddresspinshighorlow

to set the starting I2C serial address to which the LTC4271

responds. The chip will respond to this address plus the

next two incremental addresses. The base address of the

first four ports will be (A610A3A2A1A0)b. The second and

third groups of four ports will respond at the next two

logical addresses. Internally pulled up to VDD.

AD1 (Pin 2): Address Bit 1. See AD0.

AD2 (Pin 3): Address Bit 2. See AD0.

AD3 (Pin 4): Address Bit 3. See AD0.

AD6 (Pin 5): Address Bit 6. See AD0.

MID(Pin6):MidspanModeInput.Whenhigh,theLTC4271

acts as a midspan device. Internally pulled down to DGND.

CPD (Pin 8): Clock Transceiver Positive Input Output

(Digital). Connect to CPA through a data transformer.

LTC4271 датащи(PDF) 14 Page - Linear Technology

LTC4271 датащи(HTML) 14 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

датащи скачать

ссылки URL