Package Thermal Pad

(Underside)

Top Side

Island

Thermal Via

Dia 0.020 In.

Heat

Dissipation

VSS Copper Plane

VSS Copper Plane

M0029-01

CDCP1803-EP

PARAMETER MEASUREMENT INFORMATION (continued)

Modeling the CDCP1803 with a standard 4-layer JEDEC board results in a 59.5°C maximum temperature with

When deploying four thermal vias (one per quadrant), the thermal flow improves significantly, yielding 42.9°C

To ensure sufficient thermal flow, it is recommended to design with four thermal vias in applications enabling all

four outputs at once.

Figure 9. Recommended Thermal Via Placement

Copyright © 2008, Texas Instruments Incorporated

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Product Folder Link(s) :CDCP1803-EP