MC34708 datasheet(79/159 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

MC34708

Functional Block Description

When considerately exceeding the maximum input of the ADC at the scaled or unscaled inputs, the reading result will return a

full scale. It has to be noted however, that this full scale does not necessarily yield a 1022 DEC reading due to the offsets and

calibration applied. The same applies for when going below the minimum input where the corresponding 0000 DEC reading may

not be returned.

7.7.2

Control

The ADC parameters are programmed by the processor via the SPI. When a reading sequence is finished, an interrupt

ADCDONEI is generated. The interrupt can be masked with the ADCDONEM bit.

The ADC is automatically calibrated every time the PMIC is powered on.

The ADC is enabled by setting ADEN bit high. The ADC can start a series of conversions through SPI programming by setting

the ADSTART bit. If the ADEN bit is low, the ADC will be disabled and in low power mode. The ADC is automatically calibrated

every time PMIC is powered.

The conversions will begin after a small analog synchronization of up to 30 microseconds, plus a programmable delay from 0

(default) up to 600

S, by programming the bits ADDLY1[3:0]. The ADDLY2[3:0] controls the delay between each of the

conversions from 0 to 600

S. ADDLY3[3:0] controls the delay after the final conversion, and is only valid when ADCONT is high.

ADDLY1, 2, and 3 are set to 0 by default.

There is a maximum of 8 conversions that will take place when the ADC is started. The register ADSELx[3:0] selects the channel

which the ADC will read and store in the ADRESULTx register. The ADC will always start at the channel indicated in ADSEL0,

and read up to and including the channel set by the ADSTOP[2:0] bits. For example, when ADSTOP[2:0] = 010, it will request

the ADC to read channels indicated in ADSEL0, ADSEL1, and ADSEL2. When ADSTOP[2:0] = 111, all eight channels

Table 68. ADC Input Specification

Parameter

Condition

Min Typ Max

Units

Source Impedance

No bypass capacitor at input

5.0

kOhm

Bypass capacitor at input 10 nF

kOhm

Table 69. ADDLYx[3:0]

ADDLYx[3:0]

Delay in

s

0000

0001

0010

0011

120

0100

160

0101

200

0110

240

0111

280

1000

320

1001

360

1010

400

1011

440

1100

480

1101

520

1110

560

1111

600

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