CD74FCT652

BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCBS734A – JULY 2000 – REVISED JULY 2000

2

POST OFFICE BOX 655303

FUNCTION TABLE

INPUTS

DATA I/O

OPERATION OR

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

A1–A8

B1–B8

FUNCTION

L

H

H or L

H or L

X

X

Input

Input

Isolation

L

H

↑↑

X

X

Input

Input

Store A and B data

X

H

↑

H or L

X

X

Input

Unspecified†

Store A, hold B

H

H

↑↑

X‡

X

Input

Output

Store A in both registers

L

X

H or L

↑

X

X

Unspecified†

Input

Hold A, store B

L

L

↑↑

XX‡

Output

Input

Store B in both registers

L

L

X

X

X

L

Output

Input

Real-time B data to A bus

L

L

X

H or L

X

H

Output

Input

Stored B data to A bus

H

H

X

X

L

X

Input

Output

Real-time A data to B bus

H

H

H or L

X

H

X

Input

Output

Stored A data to B bus

H

L

H or L

H or L

H

H

Output

Output

Stored A data to B bus and

stored B data to A bus

† The data output functions can be enabled or disabled by various level combinations at OEAB or OEBA. Data input functions

always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

‡ When select control is low, clocks can occur simultaneously if allowances are made for propagation delays from A to B (B to

A) plus setup and hold times. When select control is high, clocks must be staggered to load both registers.