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SL74HC595 датащи(PDF) 6 Page - System Logic Semiconductor

номер детали SL74HC595
подробное описание детали  8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs
PDF  10 Pages
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производитель  SLS [System Logic Semiconductor]
домашняя страница  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL74HC595 датащи(HTML) 6 Page - System Logic Semiconductor

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SL74HC595
System Logic
Semiconductor
SLS
TIMING REQUIREMENTS(C
L=50pF,Input t r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to
-55
°C
≤85°C
≤125°C
Unit
Tsu
Minimum Setup Time,Serial Data
Input A to Shift Clock (Figure 5)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
Tsu
Minimum Setup Time, Shift Clock to
Latch Clock (Figure 6)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
th
Minimum Hold Time, Shift Clock to
Serial Data Input A (Figure 5)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
Trec
Minimum Recovery Time, Reset
Inactive to Shift Clock (Figure 2)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
Tw
Minimum Pulse Width, Reset (Figure
2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
Tw
Minimum Pulse Width, Shift Clock
(Figure 1)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
Tw
Minimum Pulse Width, Latch Clock
(Figure 6)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns



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