54AC16640, 74AC16640

16BIT BUS TRANSCEIVERS

WITH 3STATE OUTPUTS

SCAS240A − JULY 1990 − REVISED APRIL 1996

5

POST OFFICE BOX 655303

POST OFFICE BOX 1443

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance per transceiver

Outputs enabled

CL = 50 pF,

f = 1 MHz

55

pF

Cpd

Power dissipation capacitance per transceiver

Outputs disabled

CL = 50 pF,

f = 1 MHz

8

pF

PARAMETER MEASUREMENT INFORMATION

50% VCC

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

50%

50%

VCC

0 V

50% VCC

50% VCC

Input

Out-of-Phase

Output

In-Phase

Output

50% VCC

VOLTAGE WAVEFORMS

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

2

× VCC

500

Ω

500

Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2

× VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

50%

50%

[ VCC

0 V

50% VCC

20% VCC

50% VCC

80% VCC

[ 0 V

VCC

GND

Open

VOLTAGE WAVEFORMS

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

2

× VCC

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.

D. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveform