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SL74HC323 датащи(PDF) 5 Page - System Logic Semiconductor

номер детали SL74HC323
подробное описание детали  8-Bit Bidirectional Universal Shift Register with Parallel I/O
PDF  7 Pages
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производитель  SLS [System Logic Semiconductor]
домашняя страница  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL74HC323 датащи(HTML) 5 Page - System Logic Semiconductor

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SL74HC323
System Logic
Semiconductor
SLS
TIMING REQUIREMENTS(C
L=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to-55°C
≤85°C
≤125°C
Unit
tsu
Minimum Setup Time, Mode Select S1
or S2 to Clock (Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tsu
Minimum Setup Time, Data Inputs SA,
SH, PA thru PH to Clock
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
th
Minimum Hold Time, Clock to Mode
Select S1 or S2 (Figure 4)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
th
Minimum Hold Time, Clock to Data
Inputs, SA, SH, PA thru PH (Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
tw
Minimum Pulse Width, Clock (Figure
1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Reset (Figure
2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns



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