AD9518-3A-PCBZ datasheet(5/64 Pages) AD

5 / 64 page

Data Sheet

AD9518-3

Rev. B | Page 5 of 64

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CHARGE PUMP (CP)

CPV is CP pin voltage; VCP is charge pump power supply voltage

ICP Sink/Source

Programmable

High Value

4.8

With CPRSET = 5.1 kΩ

Low Value

0.60

Absolute Accuracy

2.5

CPV = VCP/2 V

CPRSET Range

2.7/10

kΩ

ICP High Impedance Mode Leakage

Sink-and-Source Current Matching

0.5 < CPV < VCP − 0.5 V

ICP vs. CPV

1.5

0.5 < CPV < VCP − 0.5 V

ICP vs. Temperature

CPV = VCP/2 V

PRESCALER (PART OF N DIVIDER)

See the VCXO/VCO Feedback Divider N—P, A, B, R section

Prescaler Input Frequency

P = 1 FD

300

MHz

P = 2 FD

600

MHz

P = 3 FD

900

MHz

P = 2 DM (2/3)

200

MHz

P = 4 DM (4/5)

1000

MHz

P = 8 DM (8/9)

2400

MHz

P = 16 DM (16/17)

3000

MHz

P = 32 DM (32/33)

3000

MHz

Prescaler Output Frequency

300

MHz

A, B counter input frequency (prescaler input frequency

divided by P)

PLL DIVIDER DELAYS

Table 44)

000

Off

001

330

010

440

011

550

100

660

101

770

110

880

111

990

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge

Pump/Phase Frequency Detector

(In-Band Is Within the LBW of the PLL)

The PLL in-band phase noise floor is estimated by measuring the

in-band phase noise at the output of the VCO and subtracting

20 log(N) (where N is the value of the N divider)

At 500 kHz PFD Frequency

−165

dBc/Hz

At 1 MHz PFD Frequency

−162

dBc/Hz

At 10 MHz PFD Frequency

−151

dBc/Hz

At 50 MHz PFD Frequency

−143

dBc/Hz

PLL Figure of Merit (FOM)

−220

dBc/Hz

Reference slew rate > 0.25 V/ns; FOM + 10 log(fPFD) is an

approximation of the PFD/CP in-band phase noise (in the flat

region) inside the PLL loop bandwidth; when running closed-

loop, the phase noise, as observed at the VCO output, is increased

by 20 log(N)

PLL DIGITAL LOCK DETECT WINDOW2

Signal available at LD, STATUS, and REFMON pins when

selected by appropriate register settings

Required to Lock (Coincidence of Edges)

Selected by Register 0x017[1:0] and Register 0x018[4]

Low Range (ABP 1.3 ns, 2.9 ns)

3.5

High Range (ABP 1.3 ns, 2.9 ns)

7.5

High Range (ABP 6.0 ns)

3.5

To Unlock After Lock (Hysteresis)2

Low Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 6.0 ns)

1 REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.

2 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

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