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AD9518-3ABCPZ-RL7 датащи(PDF) 15 Page - Analog Devices |
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AD9518-3ABCPZ-RL7 датащи(HTML) 15 Page - Analog Devices |
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15 / 64 page ![]() Data Sheet AD9518-3 Rev. B | Page 15 of 64 Pin No. Input/ Output Pin Type Mnemonic Description 13 I 3.3 V CMOS SCLK Serial Control Port Data Clock Signal. 14 I 3.3 V CMOS CS Serial Control Port Chip Select, Active Low. This pin has an internal 30 kΩ pull-up resistor. 15 O 3.3 V CMOS SDO Serial Control Port. Unidirectional serial data output. 16 I/O 3.3 V CMOS SDIO Serial Control Port. Bidirectional serial data input/output. 17 I 3.3 V CMOS RESET Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor. 18 I 3.3 V CMOS PD Chip Power Down, Active Low. This pin has an internal 30 kΩ pull-up resistor. 19 O LVPECL OUT4 LVPECL Output; One Side of a Differential LVPECL Output. 20 O LVPECL OUT4 LVPECL Output; One Side of a Differential LVPECL Output. 21, 30, 31, 40 I Power VS_LVPECL Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins. 22 O LVPECL OUT5 LVPECL Output; One Side of a Differential LVPECL Output. 23 O LVPECL OUT5 LVPECL Output; One Side of a Differential LVPECL Output. 27, 34 GND GND Ground. See the description for EPAD. 28 O LVPECL OUT3 LVPECL Output; One Side of a Differential LVPECL Output. 29 O LVPECL OUT3 LVPECL Output; One Side of a Differential LVPECL Output. 32 O LVPECL OUT2 LVPECL Output; One Side of a Differential LVPECL Output. 33 O LVPECL OUT2 LVPECL Output; One Side of a Differential LVPECL Output. 36 NC No Connection. 38 O LVPECL OUT1 LVPECL Output; One Side of a Differential LVPECL Output. 39 O LVPECL OUT1 LVPECL Output; One Side of a Differential LVPECL Output. 41 O LVPECL OUT0 LVPECL Output; One Side of a Differential LVPECL Output. 42 O LVPECL OUT0 LVPECL Output; One Side of a Differential LVPECL Output. 44 O Current set resistor RSET Resistor connected here sets internal bias currents. Nominal value = 4.12 kΩ. 46 O Current set resistor CPRSET Resistor connected here sets the CP current range. Nominal value = 5.1 kΩ. 47 I Reference input REFIN (REF2) Along with REFIN, this is the self-biased differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF2. 48 I Reference input REFIN (REF1) Along with REFIN, this is the self-biased differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1. EPAD GND GND Ground. The external paddle on the bottom of the package must be connected to ground for proper operation. |
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