SL74HC175 datasheet(4/5 Pages) SLS

4 / 5 page

SL74HC175

System Logic

Semiconductor

SLS

AC ELECTRICAL CHARACTERISTICS(C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

°C to

-55

°C

≤85°C

≤125°C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

2.0

4.5

6.0

4.8

4.0

MHz

tPLH, tPHL

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

2.0

4.5

6.0

150

190

225

tPHL, tPLH

Maximum Propagation Delay , Reset to Q or Q

(Figures 2 and 4)

2.0

4.5

6.0

125

155

190

tTLH, tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

2.0

4.5

6.0

110

CIN

Maximum Input Capacitance

Power Dissipation Capacitance (Per Flip-Flop)

Typical @25

°C,V

CC=5.0 V

CPD

Used to determine the no-load dynamic power

consumption: PD=CPDVCC

2f+I

CCVCC

TIMING REQUIREMENTS (C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

°C to

-55

°C

≤85°C

≤125°C

Unit

tSU

Minimum Setup Time, Data to

Clock (Figure 3)

2.0

4.5

6.0

100

125

150

Minimum Hold Time, Clock to

Data (Figure 3)

2.0

4.5

6.0

trec

Minimum Recovery Time,

Reset Inactive to Clock (Figure

2.0

4.5

6.0

100

125

150

Minimum Pulse Width, Clock

(Figure 1)

2.0

4.5

6.0

100

120

Minimum Pulse Width, Reset

(Figure 2)

2.0

4.5

6.0

100

120

tr, tf

Maximum Input Rise and Fall

Times (Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

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