SL74HC109

System Logic

Semiconductor

SLS

Dual J -K Flip-Flop with Set and Reset

High-Performance Silicon-Gate CMOS

The SL74HC109 is identical in pinout to the LS/ALS109. The device

inputs are compatible with standard CMOS outputs, with pullup

resistors, they are compatible with LS/ALSTTL outputs.

This device consists of two J-K flip-flops with individual set, reset,

and clock inputs. Changes at the inputs are reflected at the outputs

with the next low-to-high transition of the clock. Both Q to Q outputs

are available from each flip-flop.

ORDERING INFORMATION

SL74HC109N Plastic

SL74HC109D SOIC

PIN ASSIGNMENT

FUNCTION TABLE

Inputs

Outputs

Set

Reset

Clock

J

K

Q

Q

L

H

X

X

X

H

L

H

L

X

X

X

L

H

L

L

X

X

X

H

*

H

*

H

H

L

L

L

H

H

H

H

L

Toggle

H

H

L

H

No Change

H

H

H

H

H

L

H

H

L

X

X

No Change

X = Don’t care

*

Both outputs will remain high as long as Set and

Reset are low, but the output states are

unpredictable if Set and Reset go high

simultaneously.

LOGIC DIAGRAM

PIN 8 = GND