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SL1062A датащи(PDF) 2 Page - System Logic Semiconductor

номер детали SL1062A
подробное описание детали  Low Voltage Transmission Circuit with Dialler Interface
PDF  9 Pages
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производитель  SLS [System Logic Semiconductor]
домашняя страница  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL1062A датащи(HTML) 2 Page - System Logic Semiconductor

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SL1062A
System Logic
Semiconductor
SLS
PIN DESCRIPTION
Pin No
Designation
Description
1
LN
positive line terminal
2
GAS1
gain adjustment; transmitting amplifier
3
GAS2
gain adjustment; transmitting amplifier
4
QR
non-inverting output; receiving amplifier
5
GAR
gain adjustment; receiving amplifier
6
MIC-
inverting microphone input
7
MIC+
non-inverting microphone input
8
STAB
current stabilizer
9
VEE
negative line terminal
10
IR
receiving amplifier input
11
DTMF
dual-tone multi-frequency input
12
MUTE
mute input
13
VCC
possitive supply decoupling
14
REG
voltage regulator decoupling
15
AGC
automatic gain control input
16
SLPE
slope (DC resistance) adjustment
FUNCTIONAL DESCRIPTION
Supplies VCC, LN, SLPE, REG and STAB
Power for the IC and its peripheral circuits is usually
obtained from the telephone line. The supply voltage
is derived from the line via a dropping resistor and
regulated by the IC. The supply voltage VCC may also
be used to supply external circuits e.g. dialling and
control circuits.
Decoupling of the supply voltage is performed by a
capacitor between VCC and VEE. The internal voltage
regulator is decoupled by a capacitor between REG
and VEE.
The DC current flowing into the set is determined by
the exchange supply voltage Vexch, the feeding bridge
resistance Rexch and the DC resistance of the
telephone line Rline.
The circuit has an internal current stabilizer operating
at a level determined by a 3.6 K
Ω resistor connected
between STAB and VEE (see Fig.1).
Figure 1. Supply arrengement
When the line current (Iline) is more than 0.5 mA
greater than the sum of the IC supply current (ICC)
and the current draw by the peripheral circuitry
connected to VCC (Ip) the excess current is shunted to
VEE via LN.
The regulated voltage on the line terminal (VLN) can
be calculated as:
VLN = Vref + ISLPE x R9
VLN = Vref + ((Iline - ICC - 0.5 x 10
-3 A)-I
p) x R9



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