DS_8024RN_020

73S8024RN Data Sheet

Rev. 2

11

The following steps show the activation sequence and the timing of the card control signals when the

system controller pulls the CMDVCC low while the RSTIN is high:

•

CMDVCC

is set low.

•

•

•

•

not set RST high until 42000 clock cycles after the start of CLK.

CMDVCC

VCC

I/O

CLK

RSTIN

RST

Figure 3: Activation Sequence – RSTIN High When CMDVCCB Goes Low