MPC5554 datasheet(44/58 Pages) FREESCALE

номер детали	MPC5554

подробное описание детали	Microcontroller

PDF	58 Pages

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производитель	FREESCALE [Freescale Semiconductor, Inc]

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MPC5554 Microcontroller Data Sheet, Rev. 4

Electrical Characteristics

Freescale Semiconductor

3.13.9

eQADC SSI Timing

Figure 27. EQADC SSI Timing

Table 27. EQADC SSI Timing Characteristics

Spec

Rating

Symbol

Minimum

Typical

Maximum

Unit

FCK period (tFCK = 1  fFCK)

1, 2

1 SS timing specified at V

DDEH = 3.0–5.25 V, TA = TL to TH, and CL = 25 pF with SRC = 0b11. Maximum operating frequency

varies depending on track delays, master pad delays, and slave pad delays.

2 FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number.

tFCK

2—

tSYS_CLK

Clock (FCK) high time

tFCKHT

tSYS_CLK  6.5

—

 (t

SYS_CLK  6.5)

Clock (FCK) low time

tFCKLT

tSYS_CLK  6.5

—

 (t

SYS_CLK  6.5)

SDS lead / lag time

tSDS_LL

–7.5

—

+7.5

SDO lead / lag time

tSDO_LL

–7.5

—

+7.5

EQADC data setup time (inputs)

tEQ_SU

—

EQADC data hold time (inputs)

tEQ_HO

1—

—

1st (MSB)

2nd

25th

26th

1st (MSB) 2nd

25th

26th

FCK

SDS

SDO

External device data sample at

SDI

EQADC data sample at

FCK falling-edge

FCK rising-edge

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