SP8528DS/01

SP8528 Micropower Sampling 12-Bit A/D Converter

© Copyright 2000 Sipex Corporation

5

The device features automatic shutdown and

will shutdown to a +0.5

µA power level as CS

is brought high (de-selected). Power is proportional

to conversion duty cycle and varies from 230

µA at 30.1 µS (Duty cycle = 100%) to

5.75

µA at 1.2 ms (Duty cycle = 2.5%).

Examples:

Conversion rate

I

Duty Cycle

30.1

µS

230

µA

100%

60.2

µS

115

µA

50%

120

µS

57.5

µA

25%

1.20 mS

5.75

µA

2.5%

The device can be configured such that it

delivers serial data MSB first requiring 15 clock

periods for a full conversion. Alternately, the

device can be programmed to deliver 12 bits of

data MSB first, followed by the same 12 bits of

data LSB first. This sequence will require 26

clock periods to complete. Please refer to the

timing diagram.

Circuit Operation

The SP8528 is a SAR converter with full

differential sampled front end, capacitive DAC,

precision comparator, SuccessiveApproximations

Register, control logic and data output register.

After the input is sampled and held the

conversion process begins. The DAC MSB is

set and its output is compared with the signal

input, if the DAC output is less than the input,

the comparator outputs a one which is latched

into the SAR and simultaneously made

available at the ADC serial output pin. Each bit

is tested in a similar manner until the SAR

contains a code which represents the signal input

to within +1/2 LSB. During this process the SAR

content has been shifted out of the ADC serially.

If the MSB first format was chosen, the data will

appear at the DOUT pin MSB through LSB in 15

clock periods. If LSB first data is desired, 26

SCLK’s are needed to

complete a transfer. The LSB

appears at clock 15, with

successive bits clocked out

until the MSB appears at

clock 26. All subsequent

SCLK’s with CS = 0 shift out

0. Note that the Chip Select

Bar pin must be toggled high

DESCRIPTION

The SP8528 is a 12 bit full differential sampling

ADC with a serial data interface. The ADC

samples and converts 12 bits of data in 30.1

µS

with a 5V supply voltage applied. The SP8528

will also operate at a 3.3V supply at 45.15

µS

throughput. The device automatically shuts

down to a +0.5

µA (MAX) level as soon as the

chip is deselected (CS=1). Serial data output is

available in an MSB first or LSB first format.

FEATURES

The input sampling scheme is full differential,

where the maximum full scale range is V

signal is applied between +IN and -IN. The

signals applied at each input may both be

dynamic. This is in contrast with pseudo

differential devices which must have input low

held at a constant level during conversion. The

converter will provide significant common mode

rejection because of the full differential

sampling. Each input independently must

remain between ground and Vcc to avoid

clamping the inputs. For proper conversion the

differential input (+IN - -IN) must be less than

or equal to Vref.

The device uses a capacitive DAC architecture

which provides the sampling behavior. This

results in full Nyquist performance at the

fastest throughput rate (33.2kHz) the device is

capable of.

The power supply voltage is variable from 3.0V

to 5.5V which provides supply flexibility. At the

5.0V supply level, conversion plus sampling

time is 30.1

µS and supply current is 230 µA

(1.15 mW). With a 3.3V supply the conversion

plus sampling time is 45.15

µS and current is

reduced to 80

µA (0.26 mW).

INPUT VOLTAGE

INPUT VOLTAGE

OUTPUT

(+IN - -IN)

AT V

CODE

0 LSB

0V

000000000000

1 LSB

0.00122V

000000000001

2048 LSB

2.5000V

100000000000

4094 LSB

4.9976V

111111111110

4095 LSB

4.9988V

111111111111

ADC TRANSFER FUNCTION