SP8527 datasheet(5/12 Pages) SIPEX

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SP8527DS/01

SP8527 Micropower Sampling 10-Bit A/D Converter

The device features automatic shutdown and

will shutdown to a +0.5

µA power level as CS

is brought high (de-selected). Power is propor-

tional to conversion duty cycle and varies from

230

µA at 26.1 µS (Duty cycle = 100%) to

5.75

µA at 1.04 ms (Duty cycle = 2.5%).

Examples:

Conversion rate

CC @ 5V

Duty Cycle

26.1

µS

230

µA

100%

52.2

µS

115

µA

50%

104

µS

57.5

µA

25%

1.04 mS

5.75

µA

2.5%

The device is configured such that it

delivers serial data MSB first requiring 13 clock

periods for a full conversion. Please refer to the

timing diagram.

Circuit Operation

The SP8527 is a SAR converter with full

differential sampled front end, capacitive DAC,

precision comparator, Successive Approxima-

tions Register, control logic and data output reg-

ister. After the input is sampled and held the

conversion process begins. The DAC MSB is

set and its output is compared with the signal

input, if the DAC output is less than the input,

the comparator outputs a one which is latched

into the SAR and simultaneously made

available at the ADC serial output pin. Each bit

is tested in a similar manner until the SAR

contains a code which represents the signal input

to within +1/2 LSB. During this process the SAR

content has been shifted out of the ADC serially.

The data appears at the DOUT pin MSB through

LSB in 13 clock periods. Note that the Chip

Select Bar pin must be toggled high between

conversions. The DOUT pin will be in a high

impedance state whenever Chip Select Bar is high.

After Chip Select Bar has been toggled and brought

low again, the converter begins a new conversion.

DESCRIPTION

The SP8527 is a 10 bit full differential

sampling ADC with a serial data interface. The

ADC samples and converts 10 bits of data in

26.1

µS with a 5V supply voltage applied. The

SP8527 will also operate at a 3.3V supply at

39.2

µS throughput. The device automatically

shuts down to a +0.5

µA (MAX) level as soon

as the chip is deselected (CS=1). Serial data

output is available in an MSB first format.

FEATURES

The input sampling scheme is full differential,

where the maximum full scale range is V

REF. The

signal is applied between +IN and -IN. The

signals applied at each input may both be

dynamic. This is in contrast with pseudo differ-

ential devices which must have input low held

at a constant level during conversion. The

converter will provide significant common mode

rejection because of the full differential

sampling. Each input independently must

remain between ground and Vcc to avoid

clamping the inputs. For proper conversion the

differential input (+IN - -IN) must be less than

or equal to Vref.

The device uses a capacitive DAC architecture

which provides the sampling behavior. This

results in full Nyquist performance at the

fastest throughput rate (38.3kHz) the device is

capable of.

The power supply voltage is variable from 3.0V

to 5.5V which provides supply flexibility. At the

5.0V supply level, conversion plus sampling

time is 26.1

µS and supply current is 230 µA

(1.15 mW). With a 3.3V supply the conversion

plus sampling time is 39.2

µS and current is

reduced to 80

µA (0.26 mW).

INPUT VOLTAGE

OUTPUT

(+IN - -IN)

AT V

REF = 5V

CODE

0 LSB

0000000000

1 LSB

0.0049V

0000000001

512 LSB

2.5000V

1000000000

1022 LSB

4.9902V

1111111110

1023 LSB

4.9951V

1111111111

ADC TRANSFER FUNCTION

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