SP574BA datasheet(9/15 Pages) SIPEX

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SP574B/674B/1674B/774B

12–Bit Sampling A/D Converters

Conversion Length

A conversion start transition latches the state of A

as shown in Figure 4 and Table 1. The latched state

determines if the conversion stops with 8–bits (A

high) or continues for 12–bits (A

0 low). If all 12–

bits are read following an 8–bit conversion, the

three LSB’s will be a logic “0” and DB

3 will be a

logic “1”. A

0 is latched because it is also involved

in enabling the output buffers as explained else-

where. No other control inputs are latched.

Stand–Alone Operation

The simplest interface is a control line connected

to R/C. The other controls must be tied to known

states as follows: CE and 12/8 are wired high, A

and CS are wired low. The output data arrives in

words of 12–bits each. The limits on R/C duty

cycle are shown in Figures 8 and 9. The duty cycle

may be within and including the extremes shown

in the specifications. In general, data may be read

when R/C is high unless STS is also high, indicat-

ing a conversion is in progress.

Reading Output Data

The output data buffers remain in a high imped-

ance state until the following four conditions are

met: R/C is high, STS is low, CE is high and CS is

low. The data lines become active in response to

these four conditions, and output data according to

the conditions of the control lines 12/8 and A

0. The

timing diagram for this process is shown in Figure

7. When 12/8 is high, all 12 data outputs become

active simultaneously and the A

0 input is ignored.

The 12/8 input is usually tied high or low; it is TTL/

CMOS compatible. When 12/8 is low, the output

is separated into two 8–bit bytes as shown below:

BYTE 1

BYTE2

xxxx xxxx

xxxx 0000

MSB

LSB

This configuration makes it easy to connect to an

8–bit data bus as shown in Figure 5. The A

0 control

can be connected to the least significant bit of the

address bus in order to store the output data into

two consecutive memory locations. When A

0 is

pulled low, the 8 MSB’s are enabled only. When

0 is high, the 8 MSB’s are disabled, bits 4 through

7 are forced to a zero and the four LSB’s are

enabled. The two byte format is “left justified data”

as shown above and can be considered to have a

decimal point or binary to the left of byte 1.

shown in Table 1, and the internal control logic is

shown in a simplified schematic in Figure 4.

Conversion Start

A conversion may be initiated by a logic transition

on any of the three inputs: CE, CS R/C, as shown

in Table 1. The last of the three to reach the correct

state starts the conversion, so one, two or all three

may be dynamically controlled. The nominal de-

lay from each is the same and all three may change

state simultaneously. In order to assure that a

particular input controls the start of conversion, the

other two should be setup at least 50ns earlier.

Refer to the convert mode timing specifications.

The Convert Start timing diagram is shown in

Figure 6.

The output signal STS is the status flag and goes

high only when a conversion is in progress.

While STS is high, the output buffers remain in

a high impedance state so that data can not be

read. Also, when STS is high, an additional Start

Convert will not reset the converter or reinitiate

a conversion. Note, if A

0 changes state after a

conversion begins, an additional Start Convert

command will latch the new state of A

0 and

possibly cause a wrong cycle length for that

conversion (8–versus 12–bits).

Table 1. SPx74B Control Input Truth Table

CE CS R/C 12/8 A

OPERATION

xxxx

None

Initiate 12–Bit Conversion

Initiate 8–Bit Conversion

Initiate 12–Bit Conversion

Initiate 8–Bit Conversion

Initiate 12–Bit Conversion

Initiate 8–Bit Conversion

Enable 12–Bit Output

0100

Enable 8 MSB's Only

0101

Enable 4 LSB's plus 4

Trailing Zeroes

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