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SP319DS/08

SP319 20Mbps, +5V-Only V.35 Interface with RS-232 (V.28) Control Lines

© Copyright 2000 Sipex Corporation

Since both V+ and V- are separately generated

from Vcc in a no load condition, V+and V- will

be symmetrical. Older charge pump approaches

that generate V- from V+ will show a decrease

in the magnitude of V- compared to V+ due to

the inherent inefficiencies in design.

The clock rate for the charge pump typically

operates at 15kHz with 0.1

µF, 16V external

capacitors.

Shutdown Mode

The SP319 can be put into a low power

shutdown mode by bringing both TS000 (pin 3)

and ENV35 (pin 9) low. In shutdown mode,

SP319 draws less than 2mA. For normal

operation, both pins should be connected to +5V.

Termination Enable

The SP319 includes a termination enable pin

that connects or disconnects the receiver input

termination circuitry. A TTL logic LOW at ENT

(pin 75) will connect the "Y" termination network

to the V.35 receiver inputs. A TTL logic HIGH

at ENT (pin 75) will disconnect the "Y" termi-

nation network and the receivers will operate as

V.11 compliant receivers. The ENT pin has an

internal pull-down resistor so that a floating

input will enable the termination network. The

SP319 is compatible with the SP320 since pin

75 on the SP320 is designated as a no connect.

External Power Supplies

For applications where separate external

supplies can be applied at the V+ and V- pins.

The value of the external supply voltages should

not exceed +10V. It is critical the external power

supplies provide a power supply sequence of :

+10V, +5V, and then -10V.

Applications Information

The SP319 is a single chip device that can

implement a complete V.35 interface. Three (3)

V.35 drivers and three (3) V.35 receivers are

used for clock and data signals and four (4)

RS-232 (V.28) drivers and four (4) RS-232

(V.28) receivers can be used for the control

signals of the interface. Figures 25 and 28

show the SP319 configured in DTE and DCE

applications along with an ISO-2593 pin out.

+10V

a) C

2

+

GND

GND

b) C

2

–

–10V

Figure 20. Charge Pump Waveforms

Figure 20 shows the waveforms on the positive

and negative sides of capacitor C2 respectively.

A free-running oscillator controls the four

phases of the voltage shifting. A description

of each phase follows.

Phase 1: V

During this phase of the clock cycle, the positive

side of capacitors C1 and C2 are charged to

+5V. C1+ is switched to ground and the charge

on C1- is transferred to C2-. Since C2+ is

connected to +5V, the voltage potential across

capacitor C2 becomes 10V.

Phase 2: V

Phase two of the clock connects the negative

terminal of C2 to the Vss storage capacitor

and the positive terminal of C2 to ground,

and transfers the generated -10V to C3.

Simultaneously, the positive side of capacitor

C1 is switched to +5V and the negative side

is connected to ground.

Phase 3: V

The third phase of the clock is identical to

the first phase - the transferred charge on C1

produces -5V on the negative terminal of C1,

which is applied to the negative side of

capacitor C2. Since C2+ is at +5V, the voltage

potential across C2 is +10V.

Phase 4: V

The fourth phase of the clock connects the

negative terminal of C2 to ground and transfers

the generated +10V across C2 to C4, the Vdd

storage capacitor. The positive side of capacitor

C1 is switched to +5V and the negative side is

connected to ground, and the cycle begins again.