MKG-16487 Ver. 5.0

11

Qualcomm Atheros, Inc.

MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION

AR4100 System in Package 802.11n– General Availability Data Sheet

WiFi Functional Description

3.3.2

Reset Sequence

After a COLD_RESET event (e.g., host deasserts AR4100_CHIP_PWD_L) the AR4100 enters

the HOST_OFF state. From that point the reset sequence is as shown:

1. The host writes the enable bit in the SPI_CONFIG register via the GSPI.

2. This bring the chip to a WAKEUP transient state from where it goes to an ON state (after the

PLL clock has stabilized).

3. The ROM code executes the HOST_PROXY, which waits for the host to indicate whether to

continue loading and executing firmware or whether to enter a boot message interface (BMI)

state. The former is the normal mode; BMI is typically used to continue the host driving the

AR4100 via BMI messages. BMI allows loading alternate firmware images into the RAM

(e.g., to update the firmware in NVMEM, or run alternate firmware images for special tests).

4. If the host writes a special memory location (variable) to indicate that the firmware is to

continue being loaded from host, then it does so and executes the loaded firmware. It

eventually sends a WMIREADY event to the host

5. The host can now send further WMI commands.

3.4 Power Transition

The AR4100 provides integrated power management and control functions and extremely low

power operation for maximum battery life across all operational states by:



Gating clocks for logic when not needed



Shutting down unneeded high speed clock sources



Reducing voltage levels to specific blocks in some states

3.4.1

Hardware Power States

AR4100 hardware has five top-level hardware power states managed by the RTC block. Table 3-1

describes the power states.

3.4.2

Sleep State Management

Sleep state minimizes power consumption while saving system states. In SLEEP state, all high

speed clocks are gated off and the external reference clock source is powered off. For the AR4100

to enter SLEEP state, the MAC, and CPU systems must not be active.

The system remains in sleep state until a WAKEUP event causes the system to enter WAKEUP

state, wait for the reference clock source to stabilize, and then ungate all enabled clock trees. The

CPU wakes up only when an interrupt arrives, which may have also generated the system

WAKEUP event.