LTC4265 datasheet(13/32 Pages) LINER

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LTC4270/LTC4271

42701fb

pin Functions

LTC4270

SENSEn (Pins 1, 4, 8, 11, 15, 18, 21, 24, 30, 33, 37,

40): Port n Current Sense Input. SENSEn monitors the

external MOSFET current via a 0.5Ω or 0.25Ω sense

resistor between SENSEn and VEE. Whenever the voltage

acrossthesenseresistorexceedstheovercurrentdetection

threshold VCUT, the current limit fault timer counts up. If

the voltage across the sense resistor reaches the current

limit threshold VLIM, the GATEn pin voltage is lowered to

maintain constant current in the external MOSFET. See

Applications Information for further details. If the port is

unused, the SENSEn pin must be tied to VEE.

GATEn (Pins 2, 5, 9, 12, 16, 19, 22, 25, 29, 32, 36, 39):

Port n Gate Drive. GATEn should be connected to the gate

of the external MOSFET for port n. When the MOSFET is

turned on, the gate voltage is driven to 12V (typ) above

VEE. During a current limit condition, the voltage at GATEn

will be reduced to maintain constant current through the

externalMOSFET.Ifthefaulttimerexpires,GATEnispulled

down, turning the MOSFET off and recording a port fault

event. If the port is unused, float the GATEn pin.

OUTn (Pins 3, 6, 10, 13, 17, 20, 23, 26, 28, 31, 35, 38):

Port n Output Voltage Monitor. OUTn should be connected

to the output port. A current limit foldback circuit limits

the power dissipation in the external MOSFET by reducing

the current limit threshold when the drain-to-source volt-

age exceeds 10V. The port n Power Good bit is set when

the voltage from OUTn to VEE drops below 2.4V (typ). A

500k resistor is connected internally from OUTn to AGND

when the port is idle. If the port is unused, the OUTn pin

must be floated.

CAP2 (Pin 7): Analog Internal 4.3V Power Supply Bypass

Capacitor. Connect 0.1µF ceramic cap to VEE.

XIO0(Pin14):GeneralPurposeDigitalInputOutput.Logic

signal between VEE and VEE + 4.3V. Internal pull up.

XIO1(Pin27):GeneralPurposeDigitalInputOutput.Logic

signal between VEE and VEE + 4.3V. Internal pull up.

AGND (Pin 34): Analog Ground. Connect AGND to the

return for the VEE supply.

VEE (Pins 41, 51, 52): Main PoE Supply Input. Connect to

a –45V to –57V supply, relative to AGND. Voltage depends

on PSE type (Type 1, Type 2 or LTPoE++.)

DNA (Pin 47): Data Transceiver Negative Input Output

(Analog). Connect to DND through a data transformer.

DPA (Pin 48): Data Transceiver Positive Input Output

(Analog). Connect to DPD through a data transformer.

CNA (Pin 49): Clock Transceiver Negative Input Output

(Analog). Connect to CND through a data transformer.

CPA (Pin 50): Clock Transceiver Positive Input Output

(Analog). Connect to CPD through a data transformer.

VSSK (Exposed Pad Pin 53): Kelvin Sense to VEE.Connect

to sense resistor common node. Do not connect directly

to VEE plane. See Layout Guide.

Common Pins

NC, DNC (LTC4271 Pins 7,13; LTC4270 Pins 42, 43, 44,

45, 46): All pins identified with “NC” or “DNC” must be

left unconnected.

LTC4271

AD0(Pin1):AddressBit0.Tietheaddresspinshighorlow

to set the starting I2C serial address to which the LTC4271

responds. The chip will respond to this address plus the

next two incremental addresses. The base address of the

first four ports will be (A610A3A2A1A0)b. The second and

third groups of four ports will respond at the next two

logical addresses. Internally pulled up to VDD.

AD1 (Pin 2): Address Bit 1. See AD0.

AD2 (Pin 3): Address Bit 2. See AD0.

AD3 (Pin 4): Address Bit 3. See AD0.

AD6 (Pin 5): Address Bit 6. See AD0.

MID(Pin6):MidspanModeInput.Whenhigh,theLTC4271

acts as a midspan device. Internally pulled down to DGND.

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