LTC2960

9

2960f

Figure 2. Dual Voltage Monitoring

The closest 1% resistor value is 34k. R3 is easily obtained

from:

R3 = 7.467MΩ

The closest 1% resistor value is 7.5MΩ. Plugging the

standard values back into the equations yields the design

Figure 2 demonstrates how the inputs can be biased

to monitor two voltages (V1, V2). In this example, four

resistors are required. Calculate each divider ratio for the

RnB

RnA

=

–1

=

0.4V

–1

In Figure 2, OUT is tied back to the MR input, making the

state of the RST output dependent upon both V1 and V2. If

V1 and V2 are both above the configured falling threshold

plus hysteresis, RST is allowed to pull high. If independent

operation of the status outputs is desired, simply omit the

OUT and MR connection.

APPLICATIONS INFORMATION

ADJ

RST

OUT

MR

LTC2960-1/

LTC2960-3

R2B

V2

R2A

R1B

V1

R1A

2960 F02

SELECTING OUTPUT LOGIC STYLE

The LTC2960 status outputs are available in two options:

open-drain (LTC2960-1/LTC2960-2) or active pull-up with

The open-drain option allows the outputs to be pulled up

0

0

6

3

4.5

1.5

7.5

7.5

1.5

3

2960 F03

4.5

6

to a user defined voltage up to 36V with a resistor. The

a resistor compatible with desired output rise time and

load current specifications. Figure 3 demonstrates typical

LTC2960-1 OUT output behavior. When the status outputs

are low, power is dissipated in the pull-up resistors.

The outputs of both the LTC2960-3 and LTC2960-4 can be

configured as either low voltage active pull-up or open-

to a supply, lowers power dissipation by eliminating the

static current drawn by pull-up resistors when the outputs

are low and improves output rise time. In Figure 4(a), an

LTC2960-3 has active pull-up outputs configured by tying

are open-drain and pull-up resistors are required.

Some applications require RST and/or OUT outputs to

dition of an optional external resistor from the output to

ground. The resistor provides a path for leakage currents,

preventing the output from floating to undetermined volt-

ages when connected to high impedance (such as CMOS

logic inputs). The resistor value should be small enough to