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LTC2995

2995f

Timing of Alert Outputs

The LTC2995 has an adjustable timeout period (tUOTO)

that holds UV, OV, TO1 or TO2 asserted after any faults

have cleared. This delay will minimize the effect of input

noise with a frequency above 1/tUOTO.

A voltage monitoring example: When any VH drops below

its threshold, the UV pin asserts low. When all VH inputs

recover above their thresholds, the output timer starts. If

all inputs remain above their thresholds when the timer

finishes, the UV pin weakly pulls high. However, if any

input falls below its threshold during this timeout period,

the timer resets and restarts when all inputs are again

above the thresholds.

A temperature monitoring example: Tying PS to VCC

configures TO2 as overtemperature output. In case of

an overtemperature condition pin TO2 asserts low. The

output timer starts when the temperature crosses back

below the threshold minus the temperature hysteresis If

the temperature remains below the threshold, the timer

finishes and pin TO2 releases high.

Selecting the Timing Capacitor

The timeout period (tUOTO) for the LTC2995 is adjustable in

order to accommodate a variety of applications. Connect-

ing a capacitor, CTMR, between the TMR pin and ground

sets the timeout period. The value of capacitor needed for

a particular timeout period is:

CTMR =

tUOTO –0.5ms

8[ms / nF]

The Reset Timeout Period vs Capacitance graph found in

the Typical Performance Characteristics section shows the

desired delay time as a function of the value of the timer

capacitor that should be used. Leaving the TMR pin open

with no external capacitor generates a timeout period of

approximately 500μs. For long timeout periods, the only

limitation is the availability of a large value capacitor with

low leakage. Capacitor leakage current must not exceed

the minimum TMR charging current of 1.5μA.

Tying the TMR pin to VCC will bypass the timeout period

and no delay will occur.

Digital Output Characteristics

The DC characteristics of the UV, OV, TO1 and TO2 pull-up

and pull-down strength are shown in the Typical Perfor-

mance Characteristics section. Each pin has a weak 400kΩ

internal pull-up to VCC and a strong pull-down to ground

and can be pulled above VCC.

This arrangement allows these pins to have open-drain

behavior while possessing several other beneficial char-

acteristics. The weak pull-up eliminates the need for an

external pull-up resistor when the rise time on the pin is

not critical. On the other hand, the open drain configuration

allows for wired-OR connections and can be useful when

more than one signal needs to pull-down on the output.

At VCC = 1V, the weak pull-up current is barely turned on.

Therefore, an external pull-up resistor of no more than

100k is recommended on the pin if the state and pull-up

strength of the pin is crucial at very low VCC.

Note however, by adding an external pull-up resistor, the

pull-up strength on the pin is increased. Therefore, if it

is connected in a wired-OR connection, the pull-down

strength of any single device needs to accommodate this

additional pull-up strength.

Output Rise and Fall Time Estimation

The UV, OV, TO1 and TO2 outputs have strong pull-down

capability. The following formula estimates the output fall

time (90% to 10%) for a particular external load capaci-

tance (CLOAD):

tFALL ≈ 2.2 • RPD • CLOAD

where RPD is the on-resistance of the internal pull-down

transistor estimated to be typically 40Ω at VDD > 1V and

at room temperature (25°C), and CLOAD is the external

load capacitance on the pin. Assuming a 150pF load

capacitance, the fall time is about 13ns. The rise time on

the UV, OV, TO1 and TO2 pins is limited by a 400k pull-up

resistance to VDD. A similar formula estimates the output

rise time (10% to 90%):

tRISE ≈ 2.2 • RPU • CLOAD

where RPU is the pull-up resistance.

APPLICATIONS INFORMATION

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