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LT1674 датащи(PDF) 4 Page - Linear Technology |
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LT1674 датащи(HTML) 4 Page - Linear Technology |
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4 / 24 page ![]() LTC3109 4 3109fa TYPICAL PERFORMANCE CHARACTERISTICS ELECTRICAL CHARACTERISTICS board layout, the rated thermal package thermal resistance and other environmental factors. The junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) according to the formula: TJ = TA + (PD • θJA°C/W), where θJA is the package thermal impedance. Note 3: Specification is guaranteed by design and not 100% tested in production. Note 4: Current measurements are made when the output is not switching. Note 5: Failure to solder the exposed backside of the QFN package to the PC board ground plane will result in a thermal resistance much higher than 37°C/W. Note 6: The Absolute Maximum Rating is a DC rating. Under certain conditions in the applications shown, the peak AC voltage on the C2A and C2B pins may exceed ±8V. This behavior is normal and acceptable because the current into the pin is limited by the impedance of the coupling capacitor. Input Resistance vs VIN Efficiency vs VIN Open-Circuit Start-Up Voltage vs Source Resistance IIN vs VIN IVOUT vs VIN VIN (mV) 10 1 10 100 1000 100 1000 3109 G01 1:100 RATIO, C1 = 1nF 1:50 RATIO, C1 = 4.7nF 1:20 RATIO, C1 = 10nF VOUT = 0V VIN (mV) 10 10 100 1000 10000 100 1000 3109 G02 1:100 RATIO, C1 = 1nF 1:50 RATIO, C1 = 4.7nF 1:20 RATIO, C1 = 10nF VOUT = 3.3V NO LOAD ON VLDO VIN (mV) 10 2.0 3.0 4.0 5.0 6.0 100 1000 3109 G03 7.0 2.5 3.5 4.5 5.5 6.5 1:100 RATIO, C1 = 1nF 1:50 RATIO, C1 = 4.7nF 1:20 RATIO, C1 = 10nF VOUT = 0V SOURCE RESISTANCE (Ω) 0 0 10 30 40 50 6789 90 3109 G05 20 12345 10 60 70 80 VIN (mV) 10 0 10 20 30 40 100 1000 3109 G04 50 5 15 25 35 45 1:100 RATIO, C1 = 1nF 1:50 RATIO, C1 = 4.7nF 1:20 RATIO, C1 = 10nF VOUT = 0V TA = 25°C, unless otherwise noted. VIN (mV) 10 0.1 1 10 100 100 1000 3109 G18 1:50 RATIO C1 = 4.7nF VOUT = 5V VOUT = 3.3V PVOUT vs VIN |
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