LTC3407-2 datasheet(21/30 Pages) LINER

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LT3510

3510fe

At power-up, a reset signal sets the soft-start latch and

discharges both SS pins to approximately 0V to ensure

proper start-up. When both SS pins are fully discharged

the latch is reset and the internal 3.25μA current source

starts to charge the SS pin.

When the SS pin voltage is below 50mV, the VC pin is pulled

low which disables switching. This allows the SS pin to be

used as an individual shutdown for each channel.

As the SS pin voltage rises above 50mV, the VC pin is re-

leased and the output is regulated to the SS voltage. When

the SS pin voltage exceeds the internal 0.8V reference, the

output is regulated to the reference. The SS pin voltage

will continue to rise until it is clamped at 2V.

In the event of a VIN1 undervoltage lockout, the SHDN

pin driven below 1.28V, or the internal die temperature

exceeding its maximum rating during normal operation, the

soft-start latch is set, triggering a start-up sequence.

In addition, if the load exceeds the maximum output switch

current, the output will start to drop causing the VC pin

clamp to be activated. As long as the VC pin is clamped,

the SS pin will be discharged. As a result, the output will

be regulated to the highest voltage that the maximum

output current can support. For example, if a 6V output

is loaded by 1

Ω the SS pin will drop to 0.4V, regulating

the output at 3V ( 3A • 1

Ω ). Once the overload condition

is removed, the output will soft-start from the temporary

voltage level to the normal regulation point.

Since the SS pin is clamped at 2V and has to discharge

to 0.8V before taking control of regulation, momentary

overload conditions will be tolerated without a soft-start

recovery. The typical time before the SS pin takes control

is:

tSS(CONTROL) =

CSS •1.2V

700

μA

Power Good Indicators

The PG pin is the open-collector output of an internal

comparator. The comparator compares the FB pin voltage

to 90% of the reference voltage with 30mV of hysteresis.

The PG pin has a sink capability of 800μA when the FB pin

is below the threshold and can withstand 25V when the

threshold is exceeded. The PG pin is active (sink capability

is reduced in shutdown and undervoltage lockout mode)

as long as the VIN1 pin voltage exceeds 1V.

Output Tracking/Sequencing

Complex output tracking and sequencing between chan-

nels can be implemented using the LT3510’s SS and PG

pins. Figure 9 shows several conﬁgurations for output

tracking/sequencing for a 3.3V and 1.8V application.

Independent soft-start for each channel is shown in

Figure 9a. The output ramp time for each channel is set

by the soft-start capacitor as described in the soft-start

section.

Ratiometric tracking is achieved in Figure 9b by connecting

both SS pins together. In this conﬁguration, the SS pin

source current is doubled (6.5μA) which must be taken

into account when calculating the output rise time.

By connecting a feedback network from VOUT1 to the SS2

pin with the same ratio that sets VOUT2 voltage, absolute

tracking shown in Figure 9c is implemented. The minimum

value of the top feedback resistor (R1) should be set such

that the SS pin can be driven all the way to ground with

700μA of sink current when VOUT1isatitsregulatedvoltage.

In addition, a small VOUT2 voltage offset will be present

due to the SS2 3.25μA source current. This offset can be

corrected for by slightly reducing the value of R2.

Figure 9d illustrates output sequencing. When VOUT1 is

within 10% of its regulated voltage, PG1 releases the SS2

soft-start pin allowing VOUT2 to soft-start. In this case PG1

will be pulled up to 2V by the SS pin. If a greater voltage

is needed for PG1 logic, a pull-up resistor to VOUT1 can

be used. This will decrease the soft-start ramp time and

increase tolerance to momentary shorts.

If precise output ramp up and down is required, drive the

SS pins as shown in Figure 9e. The minimum value of

resistor (R3) should be set such that the SS pin can be

driven all the way to ground with 700μA of sink current

during power-up and fault conditions.

Multiple Input Voltages

For applications requiring large inductors due to high VIN

to VOUT ratios, a 2-stage step-down approach may reduce

APPLICATIONS INFORMATION

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