DM9161CI datasheet(19/47 Pages) DAVICOM

19 / 47 page

DM9161CI

10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver

Final

Version: DM9161CI-DS-F01

February 22, 2012

Figure 7-4

7.2.2 100Base-TX Receiver

The 100Base-TX receiver contains several function blocks

that convert the scrambled 125Mb/s serial data to

synchronous 4-bit nibble data, which is then provided to the

MII.

The receive section contains the following functional blocks:

- Signal Detect

- Adaptive Equalizer

- MLT-3 to NRZI Decoder

- Clock Recovery Module

- NRZI to NRZ Decoder

- Serial to Parallel

- Descrambler

- Code Group Alignment

- 4B5B Decoder

7.2.2.1 Signal Detect

The signal detects function meets the specifications

mandated by the ANSI XT12 TP-PMD 100Base-TX

Standards for both voltage thresholds and timing

parameters.

7.2.2.2 Adaptive Equalizer

When transmitting data at high speeds over copper twisted

pair cable, attenuation based on frequency becomes a

concern. In high speed twisted pair signaling, the frequency

content of the transmitted signal can vary greatly during

normal operation based on the randomness of the

scrambled data stream. This variation in signal attenuation

caused by frequency variations must be compensated for to

ensure the integrity of the received data. In order to ensure

quality transmission when employing MLT-3 encoding, the

compensation must be able to adapt to various cable

lengths and cable types depending on the installed

environment. The selection of long cable lengths for a given

implementation requires significant compensation, which will

be over-kill in a situation that includes shorter, less

attenuating cable lengths. Conversely, the selection of short

or intermediate cable lengths requiring less compensation

will cause serious under-compensation for longer length

cables. Therefore, the compensation or equalization must

be adaptive to ensure proper conditioning of the received

signal independent of the cable length.

7.2.2.3 MLT-3 to NRZI Decoder

The DM9161CI decodes the MLT-3 information from the

Digital Adaptive Equalizer into NRZI data. The relation

between NRZI and MLT-3 data is shown in figure 7-4.

7.2.2.4 Clock Recovery Module

Binary

Common

driver

Binary minus

Binary plus

MLT-3

Binary

DM9161CI датащи(PDF) 19 Page - Davicom Semiconductor, Inc.

DM9161CI датащи(HTML) 19 Page - Davicom Semiconductor, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

датащи скачать

ссылки URL