DM9010BIEP datasheet(9/60 Pages) DAVICOM

9 / 60 page

DM9010BI

Industrial-temperature Single Chip Ethernet Controller with General Processor Interface

Preliminary

Version: DM9010BI--DS-P01

January 12, 2010

5. PIN DESCRIPTION

I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, P= Power,

LI= reset Latch Input, #= asserted low, PD=internal pull-low about 60K ohm, PU=internal pull-high

5.1 MII Interface

Pin No.

Pin Name

I/O

Description

LINK_I

I,PD

External MII device link status

41,40,39,

RXD [3:0]

I,PD

External MII Receive Data

4-bit nibble data input (synchronous to RXCLK) when in 10/100 Mbps. MII mode

CRS

I/O,PD External MII Carrier Sense

Active high to indicate the pressure of carrier, due to receive or transmit activities

in 10 Base-T or 100 Base-TX modes. This pin is output in reverse MII interface.

COL

I/O,PD External MII Collision Detect. This pin is output in reverse MII interface.

RX_DV

I,PD

External MII Receive Data Valid

RX_ER

I,PD

External MII Receive Error

RX_CLK

I,PD

External MII Receive Clock

TX_CLK

I/O,PD External MII Transmit Clock. This pin in output in MII interfaces.

53,52,51,

TXD [3:0]

O,PD External MII Transmit Data

4-bit nibble data outputs (synchronous to the TX_CLK) when in 10/100Mbps

nibble mode

TXD [2:0] is also used as the strap pins of IO base address.

IO base = (strap pin value of TXD [2:0]) * 10H + 300H

TX_ EN

O,PD External MII Transmit Enable

MDIO

I/O,PD MII Serial Management Data

MDC

O,PD MII Serial Management Data Clock

This pin is also used as the strap pin of the polarity of the INT pin

When the MDC pin is pulled high, the INT pin is low active; otherwise the INT pin

is high active

5.2 Processor Interface

IOR#

I,PD

Processor Read Command

This pin is low active at default; its polarity can be modified by EEPROM setting.

See the EEPROM content description for detail

IOW#

I,PD

Processor Write Command

This pin is low active at default; its polarity can be modified by EEPROM setting.

See the EEPROM content description for detail

AEN

I,PD

Address Enable

A low active signal used to select the DM9010BI.

IOWAIT

O,PD Processor Command Ready

When a command is issued before last command is completed, the IOWAIT will

be pulled low to indicate the current command is waited

The polarity and output type can be updated by EEPROM. The default is

Open-Drain output and low active.

DM9010BIEP датащи(PDF) 9 Page - Davicom Semiconductor, Inc.

DM9010BIEP датащи(HTML) 9 Page - Davicom Semiconductor, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

датащи скачать

ссылки URL