поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

ADIS16488/PCBZ датащи(PDF) 5 Page - Analog Devices

номер детали ADIS16488/PCBZ
подробное описание детали  Ten Degrees of Freedom Inertial Sensor
PDF  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADIS16488/PCBZ датащи(HTML) 5 Page - Analog Devices

  ADIS16488/PCBZ Datasheet HTML 1Page - Analog Devices ADIS16488/PCBZ Datasheet HTML 2Page - Analog Devices ADIS16488/PCBZ Datasheet HTML 3Page - Analog Devices ADIS16488/PCBZ Datasheet HTML 4Page - Analog Devices ADIS16488/PCBZ Datasheet HTML 5Page - Analog Devices ADIS16488/PCBZ Datasheet HTML 6Page - Analog Devices ADIS16488/PCBZ Datasheet HTML 7Page - Analog Devices ADIS16488/PCBZ Datasheet HTML 8Page - Analog Devices ADIS16488/PCBZ Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 36 page
background image
Data Sheet
ADIS16488
Rev. B | Page 5 of 36
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Normal Mode
Parameter
Description
Min1
Typ
Max1
Unit
fSCLK
Serial clock
0.01
15
MHz
tSTALL
Stall period between data
2
µs
tCLS
Serial clock low period
31
ns
tCHS
Serial clock high period
31
ns
t
CS
Chip select to clock edge
32
ns
tDAV
DOUT valid after SCLK edge
10
ns
tDSU
DIN setup time before SCLK rising edge
2
ns
tDHD
DIN hold time after SCLK rising edge
2
ns
tDR, tDF
DOUT rise/fall times, ≤100 pF loading
3
8
ns
tDSOE
CS assertion to data out active
0
11
ns
tHD
SCLK edge to data out invalid
0
ns
tDSHI
CS deassertion to data out high impedance
0
9
ns
t1
Input sync pulse width
5
µs
t2
Input sync to data-ready output
490
µs
t3
Input sync period
417
µs
1
Guaranteed by design and characterization, but not tested in production.
Timing Diagrams
CS
SCLK
DOUT
DIN
1
2
3
4
5
6
15
16
R/W
A5
A6
A4
A3
A2
D2
MSB
DB14
D1
LSB
DB13
DB12
DB10
DB11
DB2
LSB
DB1
tCS
tDSHI
tDAV
tHD
tCHS
tCLS
tDSOE
tDHD
tDSU
Figure 2. SPI Timing and Sequence
CS
SCLK
tSTALL
Figure 3. Stall Time and Data Rate
t3
t2
t1
SYNC
CLOCK (CLKIN)
DATA
READY
OUTPUT
REGISTERS
DATA VALID
DATA VALID
Figure 4. Input Clock Timing Diagram



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com