ADF4351BCPZ datasheet(13/28 Pages) AD

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Data Sheet

ADF4351

Rev. 0 | Page 13 of 28

The R counter output is used as the clock for the band select

logic. A programmable divider is provided at the R counter

output to allow division by an integer from 1 to 255; the divider

value is set using Bits[DB19:DB12] in Register 4 (R4). When the

required PFD frequency is higher than 125 kHz, the divide ratio

should be set to allow enough time for correct band selection.

Band selection takes 10 cycles of the PFD frequency, equal to

80 µs. If faster lock times are required, Bit DB23 in Register 3

(R3) must be set to 1. This setting allows the user to select a

higher band select clock frequency of up to 500 kHz, which

speeds up the minimum band select time to 20 µs. For phase

adjustments and small (<1 MHz) frequency adjustments, the

user can disable VCO band selection by setting Bit DB28 in

After band selection, normal PLL action resumes. The nominal

value of KV is 40 MHz/V when the N divider is driven from the

VCO output or from this value divided by D. D is the output

divider value if the N divider is driven from the RF divider output

(selected by programming Bits[DB22:DB20] in Register 4). The

ADF4351 contains linearization circuitry to minimize any vari-

ation of the product of ICP and KV to keep the loop bandwidth

constant.

The VCO shows variation of KV as the VTUNE varies within the

band and from band to band. For wideband applications cover-

ing a wide frequency range (and changing output dividers), a

value of 40 MHz/V provides the most accurate KV because this

value is closest to an average value. Figure 21 shows how KV

varies with fundamental VCO frequency, along with an average

value for the frequency band. Users may prefer this figure when

using narrow-band designs.

2.0

2.5

3.0

3.5

4.0

4.5

FREQUENCY (GHz)

Figure 21. VCO Sensitivity (KV) vs. Frequency

OUTPUT STAGE

The RFOUTA+ and RFOUTA− pins of the ADF4351 are connected

to the collectors of an NPN differential pair driven by buffered

outputs of the VCO, as shown in Figure 22.

VCO

RFOUTA+

RFOUTA–

BUFFER/

DIVIDE-BY-1/-2/-4/-8/

-16/-32/-64

Figure 22. Output Stage

To allow the user to optimize the power dissipation vs. the

output power requirements, the tail current of the differential

pair is programmable using Bits[DB4:DB3] in Register 4 (R4).

Four current levels can be set. These levels give output power

levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, using a 50 Ω

resistor to AVDD and ac coupling into a 50 Ω load. Alternatively,

both outputs can be combined in a 1 + 1:1 transformer or a 180°

microstrip coupler (see the Output Matching section).

If the outputs are used individually, the optimum output stage

consists of a shunt inductor to VVCO. The unused complementary

output must be terminated with a similar circuit to the used output.

An auxiliary output stage exists on the RFOUTB+ and RFOUTB−

pins, providing a second set of differential outputs that can be

used to drive another circuit. The auxiliary output stage can be

used only if the primary outputs are enabled. If the auxiliary

output stage is not used, it can be powered down.

Another feature of the ADF4351 is that the supply current to

the RF output stage can be shut down until the part achieves

lock, as measured by the digital lock detect circuitry. This

feature is enabled by setting the mute till lock detect (MTLD)

bit in Register 4 (R4).

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