ADE7880 datasheet(6/104 Pages) AD

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ADE7880

Data Sheet

Rev. A | Page 6 of 104

Parameter1, 2

Min

Typ

Max

Unit

Test Conditions/Comments

WAVEFORM SAMPLING

Sampling CLKIN/2048, 16.384 MHz/2048 =

8 kSPS

Current and Voltage Channels

See the

Waveform Sampling Mode

section

Signal-to-Noise Ratio, SNR

PGA = 1

Signal-to-Noise-and-Distortion Ratio,

SINAD

PGA = 1

Bandwidth (−3 dB)

3.3

kHz

TIME INTERVAL BETWEEN PHASES

Measurement Error

0.3

Degrees

Line frequency = 45 Hz to 65 Hz, HPF on

CF1, CF2, CF3 PULSE OUTPUTS

Maximum Output Frequency

68.818

kHz

WTHR = VARTHR = VATHR = 3

Duty Cycle

If CF1, CF2, or CF3 frequency > 6.25 Hz and

CFDEN is even and > 1

(1 + 1/CFDEN) ×

If CF1, CF2, or CF3 frequency > 6.25 Hz and

CFDEN is odd and > 1

Active Low Pulse Width

If CF1, CF2, or CF3 frequency < 6.25 Hz

Jitter

0.04

For CF1, CF2, or CF3 frequency = 1 Hz and

nominal phase currents are larger than

10% of full scale

REFERENCE INPUT

REFIN/OUT Input Voltage Range

1.1

1.3

Minimum = 1.2 V − 8%; maximum =

1.2 V + 8%

Input Capacitance

ON-CHIP REFERENCE

Nominal 1.21 V at the REFIN/OUT pin at

TA = 25°C

PSM0 and PSM1 Modes

Reference Error

±2

Output Impedance

kΩ

Temperature Coefficient

ppm/°C

CLKIN

All specifications CLKIN of 16.384 MHz

Input Clock Frequency

16.22

16.384

16.55

MHz

Crystal Equivalent Series Resistance

200

CLKIN Load Capacitor4

CLKOUT Load Capacitor4

LOGIC INPUTS—MOSI/SDA, SCLK/SCL, SS,

RESET, PM0, AND PM1

Input High Voltage, VINH

2.4

VDD = 3.3 V ± 10%

Input Current, IIN

Input = VDD = 3.3 V

Input Low Voltage, VINL

0.8

VDD = 3.3 V ± 10%

Input Current, IIN

−7.3

μA

Input = 0, VDD = 3.3 V

Input Capacitance, CIN

LOGIC OUTPUTS—IRQ0, IRQ1, AND

MISO/HSD

VDD = 3.3 V ± 10%

Output High Voltage, VOH

3.0

VDD = 3.3 V ± 10%

ISOURCE

800

μA

Output Low Voltage, VOL

0.4

VDD = 3.3 V ± 10%

ISINK

CF1, CF2, CF3/HSCLK

Output High Voltage, VOH

2.4

VDD = 3.3 V ± 10%

ISOURCE

500

μA

Output Low Voltage, VOL

0.4

VDD = 3.3 V ± 10%

ISINK

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