Data Sheet

AD5737

Rev. B | Page 25 of 44

DATA REGISTERS

The input shift register is 24 bits wide. When PEC is enabled,

the input shift register is 32 bits wide, with the last eight bits

corresponding to the PEC code (see the Packet Error Checking

section for more information about PEC). When writing to a

data register, the format shown in Table 10 must be used.

DAC Data Register

When writing to a DAC data register, Bit D15 to Bit D4 are the

DAC data bits. Table 12 shows the register format, and Table 11

describes the functions of Bit D23 to Bit D16.

Table 10. Input Shift Register for a Write Operation to a Data Register

MSB

LSB

D23

D22

D21

D20

D19

D18

D17

D16

D15 to D0

R/W

DUT_AD1

DUT_AD0

DREG2

DREG1

DREG0

DAC_AD1

DAC_AD0

Data

Table 11. Descriptions of Data Register Bits[D23:D16]

Bit Name

Description

R/W

This bit indicates whether the addressed register is written to or read from.

0 = write to the addressed register.

1 = read from the addressed register.

DUT_AD1, DUT_AD0

Used in association with the external pins AD1 and AD0, these bits determine which AD5737 device is being

addressed by the system controller.

DUT_AD1

DUT_AD0

Part Addressed

0

0

Pin AD1 = 0, Pin AD0 = 0

0

1

Pin AD1 = 0, Pin AD0 = 1

1

0

Pin AD1 = 1, Pin AD0 = 0

1

1

Pin AD1 = 1, Pin AD0 = 1

DREG2, DREG1, DREG0

These bits select the register to be written to. If a control register is selected (DREG[2:0] = 111), the CREG bits in

the control register select the specific control register to be written to (see Table 19).

DREG2

DREG1

DREG0

Function

0

0

0

Write to DAC data register (one DAC channel)

0

0

1

Reserved

0

1

0

Write to gain register (one DAC channel)

0

1

1

Write to gain registers (all DAC channels)

1

0

0

Write to offset register (one DAC channel)

1

0

1

Write to offset registers (all DAC channels)

1

1

0

Write to clear code register (one DAC channel)

1

1

1

Write to a control register

DAC_AD1, DAC_AD0

These bits are used to specify the DAC channel. If a write to the part does not apply to a specific DAC channel,

these bits are don’t care bits.

DAC_AD1

DAC_AD0

DAC Channel

0

0

DAC A

0

1

DAC B

1

0

DAC C

1

1

DAC D

Table 12. Programming the DAC Data Register

D23

D22

D21

D20

D19

D18

D17

D16

D15 to D4

D3 to D0

R/W

DUT_AD1

DUT_AD0

0

0

0

DAC_AD1

DAC_AD0

DAC data

X1

1

X = don’t care.