CLC3800 datasheet(13/17 Pages) CADEKA

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Data Sheet

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Figure 3. Typical Output Configuration

Power Supply Decoupling

For optimum performance, power supply decoupling

is required. Figure 4 shows the recommended usage

of power supply decoupling capacitors.

The 0.1µF

decoupling capacitor must be placed as close to pin 4 as

possible, < 0.1” or < 2.5mm, to be effective. The larger,

1µF capacitor can be placed further away.

Figure 4. Recommended Power Supply Decoupling

0.5

1.5

2.5

-40

-20

Ambient Temperature (°C)

SOIC-8

Figure 5. Maximum Power Derating

Power Dissipation Considerations with DC-Coupled Loads

When driving DC loads, the supply current is much higher

than in AC applications and care must be taken to dissipate

the extra heat generated. The output signal will swing

from about 0.3V to 2.3V for full swing video. In the worst

case condition, an all white screen with dual DC loads,

the additional thermal rise over the quiescent condition is

about 20°C. An easy way to help distribute this extra heat

is to place a ground plane under the part and add ground

plane on the bottom of the board immediately under the

part with vias between the two planes.

The CLC3800 is designed primarily for low voltage

operation with supply values between 3.0V and 5.5V, but

larger supplies can be used. In this situation, DC loads

may not be possible due to thermal considerations. With

single DC loads on all three channels and a 12V supply,

the thermal rise is an additional 45° this gives a total

temperature rise of about 57°.

Layout Considerations

General layout and supply bypassing play major roles

in high frequency performance. CaDeKa has evaluation

boards to use as a guide for high frequency layout and as

aid in device testing and characterization. Follow the steps

below as a basis for high frequency layout:

• Include 1µF and 0.1µF ceramic capacitors for power

supply decoupling

• Place the 6.8µF capacitor <0.75 inches of the power pin

• Place the 0.1µF capacitor <0.1 inches of the power pin

• Remove the ground plane near the input and output

pins to reduce parasitic capacitance

• Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts for more information.

Evaluation Board Information

The following evaluation boards are available to aid in the

testing and layout of these devices:

Evaluation Board

Products

CEB021

CLC3800, CLC3801 in SOIC pack-

ages

220µF

CLC3800

IN1

OUT1

IN2

IN3

OUT3

+Vs

OUT2

GND

75Ω

220µF

75Ω

Video Cables

AC-Coupling Caps

are Optional

75Ω

CLC3800

IN1

OUT1

IN2

IN3

OUT3

+Vs

OUT2

GND

+3V or +5V

0.1µF

1.0µF

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