CLC1201 datasheet(11/15 Pages) CADEKA

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Data Sheet

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Application Information

Basic Operation

The CLC1201 is a monolithic instrumentation amplifier

based on the classic three op amp solution, refer to

the Functional Block Diagram on page 1. The CLC1201

produces a single-ended output reffered to the REF pin

potential.

The internal resistors are trimmed which allows the gain to

be accurately adjusted with one external resistor RG.

49.4k

G - 1

RG =

49.4k

G =

+ 1;

RG also determines the transconductance of the

preamp stage. As RG is reduced for larger gains, the

transconductance increases to that of the input transistors.

Producing the following advantages:

▪ Open-loop gain increases as the gain is increased,

reducing gain releated errors

▪ Gain-bandwidth increases as the gain is increased,

optimizing frequency response

▪ Reduced input voltage noise which is determined by the

collector current and base resistance of the input devices

Gain Selection

The impeadance between pins 1 and 8, RG, sets the gain

of the CLC1201. Table 1 shows the required standard

table values of RG for various calculated gains. For G =

1, RG = ∞.

1% RG (Ω)

Caclulated

Gain

0.1% RG (Ω)

Calculated

Gain

49.9k

1.990

49.3k

2.002

12.4k

4.984

12.4k

4.984

5.49k

9.998

5.49k

9.998

2.61k

19.93

2.61k

19.93

1.00k

50.40

1.01k

49.91

499

100.0

499

100.0

249

199.4

249

199.4

100

495.0

98.8

501.0

49.9

991.0

49.3

1,003.0

Table 1: Recommended RG Values

Follow these guidelines for improved performance:

▪ To maintain gain accuracy, use 0.1% to 1% resistors

▪ To minimize gain error, avoid high parasitic resistance in

series with RG

▪ Tominimizegaindrift,uselowTCresistors(<10ppm/°C)

Common Mode Rejection

The CLC1201 offers high CMRR. To acheive optimal CMRR

performance:

▪ Connect the reference terminal (pin 5) to a low

impedance source

▪ Minimize capacitive and resistive differences between

the inputs

In many applications, shielded cables are used to

minimize noise. Properly drive the shield for best CMRR

performance over frequency. Figures 1 and 2 show active

data guards that are configured to improve AC common-

mode rejections. the capacitances of input cable shields

are “bootstrapped” to minimize the capacitance mismatch

between the inputs.

CLC1200

CLCxxx

+VS

Output

RG / 2

-VS

REF

RG / 2

+ Input

- Input

100

Figure 1: Common-mode Shield Driver

CLC1200

+VS

Output

-VS

REF

+ Input

- Input

100

-VS

Figure 2: Differential Shield Driver

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