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CLC1018ISO8X датащи(PDF) 12 Page - Cadeka Microcircuits LLC. |
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CLC1018ISO8X датащи(HTML) 12 Page - Cadeka Microcircuits LLC. |
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12 / 17 page ![]() Data Sheet ©2009-2011 CADEKA Microcircuits LLC www.cadeka.com 12 + - Rf Input Output Rg Rs CL RL Figure 7. Addition of RS for Driving Capacitive Loads Table 1 provides the recommended RS for various capacitive loads. The recommended RS values result in approximately <1dB peaking in the frequency response. The Frequency Response vs. CL plot, on page 4, illustrates the response of the CLCx008. CL (pF) RS (Ω) -3dB BW (kHz) 10pF 0 22 20pF 100 19 50pF 100 12 100pF 100 10.2 Table 1: Recommended RS vs. CL For a given load capacitance, adjust RS to optimize the tradeoff between settling time and bandwidth. In general, reducing RS will increase bandwidth at the expense of additional overshoot and ringing. Overdrive Recovery An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLC1008, CLC1018, and CLC2008 will typically recover in less than 20ns from an overdrive condition. Figure 8 shows the CLC1008 in an overdriven condition. Time (200ns/div) G = 5 Output Input Figure 8. Overdrive Recovery Layout Considerations General layout and supply bypassing play major roles in high frequency performance. CaDeKa has evaluation boards to use as a guide for high frequency layout and as an aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: ▪ Include 6.8µF and 0.1µF ceramic capacitors for power supply decoupling ▪ Placethe6.8µFcapacitorwithin0.75inchesofthepowerpin ▪ Placethe0.1µFcapacitorwithin0.1inchesofthepowerpin ▪ Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance ▪ Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts below for more information. Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Evaluation Board # Products CEB002 CLC1008, CLC1018 in SOT23 CEB003 CLC1008 in SOIC CEB006 CLC2008 in SOIC CEB010 CLC2008 in MSOP |
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