MICRF506BML datasheet(23/42 Pages) MICREL

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Micrel

MICRF506BML/YML

Bit Synchronizer

A6..A0

0000110

ModclkS2

ModclkS1

ModclkS0

BitSync_clkS2

BitSync_clkS1

BitSync_clkS0

BitRate_clkS2

0000111

BitRate_clkS1

BitRate_clkS0

RefClk_K5

RefClk_K4

RefClk_K3

RefClk_K2

RefClk_K1

RefClk_K0

A bit synchronizer can be enabled in receive mode

by selecting the synchronous mode (Sync_en=1).

The DataClk pin will output a clock with twice the

frequency of the bit rate (a bit rate of 20 kbit/sec

gives a DataClk of 20 kHz). A received symbol/bit on

DataIXO will be output on rising edge of DataClk.

The micro controller should therefore sample the

symbol/bit on falling edge of DataClk.

The bit synchronizer uses a clock which needs to be

programmed according to the bit rate. The clock

frequency should be 16 times the actual bit rate (a

bit rate of 20 kbit/sec needs a bit synchronizer clock

with frequency of 320 kHz). The clock frequency is

set by the following formula:

fBITSYNC_CLK

fXCO

Refclk_K

× 2(7-BITSYNC_clkS )

where

fBITSYNC_CLK:

The

bit

synchronizer

clock

frequency (16 times higher than the bit rate)

fXCO: Crystal oscillator frequency

Refclk_K: 6 bit divider, values between 1 and

BitSync_clkS: Bit synchronizer setting, values

between 0 and 7

Refclk_K is also used to derive the modulator clock

and the bit rate clock.

At the beginning of a received data package, the bit

synchronizer clock frequency is not synchronized to

the bit rate. When these two are maximum offset to

each

other,

takes

bit/symbols

before

synchronization is achieved.

July 2006

M9999-092904

+1 408-944-0800

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