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C511 датащи(PDF) 38 Page - Siemens Semiconductor Group |
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C511 датащи(HTML) 38 Page - Siemens Semiconductor Group |
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38 / 43 page ![]() Semiconductor Group 38 C511 / C513 Figure 14 SSC Timing Figure 15 External Clock Drive at XTAL1 Notes: Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is valid for the other cases accordingly. In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the falling edge of SLS (if transmitter is enabled). In the case of master mode and CPHA = 0, the MSB becomes valid after the data has been written into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition. |
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