SC403B datasheet(26/32 Pages) SEMTECH

26 / 32 page

SC403B

Applications Information (continued)

output capacitors, typically SP or POSCAP devices. For

stability the ESR zero of the output capacitor should be

lower than approximately one-third the switching fre-

quency. The formula for minimum ESR is shown by the

following equation.

OUT

MIN

Using Ceramic Output Capacitors

For applications using ceramic output capacitors, the ESR

is normally too small to meet the above ESR criteria. In

these applications it is necessary to add a small virtual ESR

network composed of two capacitors and one resistor, as

shown in Figure 14. This network creates a ramp voltage

across C

L, analogous to the ramp voltage generated across

the ESR of a standard capacitor. This ramp is then capaci-

tively coupled into the FB pin via capacitor C

COUT

Low-

side

High-

side

Virtual

ESR

Network

Figure 14 — Virtual ESR Ramp Circuit

Dropout Performance

The output voltage adjust range for continuous-conduc-

tion operation is limited by the fixed 80ns (typical)

minimum off-time of the one-shot. When working with

low input voltages, the duty-factor limit must be calcu-

lated using worst-case values for on and off times.

The duty-factor limitation is shown by the next equation.

)

MAX

(

OFF

)

MIN

(

)

MIN

(

DUTY

The inductor resistance and MOSFET on-state voltage

drops must be included when performing worst-case

dropout duty-factor calculations.

System DC Accuracy (V

OUT Controller)

Three factors affect V

OUT accuracy: the trip point of the FB

error comparator, the ripple voltage variation with line

and load, and the external resistor tolerance. The error

comparator offset is trimmed so that under static condi-

tions it trips when the feedback pin is within +1% of the

reference voltage.

The on-time pulse from the SC403B in the design example

is calculated to give a pseudo-fixed frequency of 300kHz.

Some frequency variation with line and load is expected.

This variation changes the output ripple voltage. Because

constant on-time converters regulate to the valley of the

output ripple, ½ of the output ripple appears as a DC regu-

lation error. For example, if the output ripple is 50mV with

IN = 6 volts, then the measured DC output will be 25mV

above the comparator trip point. If the ripple increases to

80mV with V

IN = 25V, then the measured DC output will be

40mV above the comparator trip. The best way to mini-

mize this effect is to minimize the output ripple.

To compensate for valley regulation, it may be desirable to

use passive droop. Take the feedback directly from the

output side of the inductor and place a small amount of

trace resistance between the inductor and output capaci-

tor. This trace resistance should be optimized so that at

full load the output droops to near the lower regulation

limit. Passive droop minimizes the required output capaci-

tance because the voltage excursions due to load steps

are reduced as seen at the load.

The use of 1% feedback resistors may result in up to 1%

error. If tighter DC accuracy is required, 0.1% resistors

should be used.

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