GaAs MMIC Low Noise Amplifier SOIC-8 Platform

Rev. V3

Application Note

M540

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4

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changes to the product(s) or information contained herein without notice.

MMIC LNA Product Customer Use

Considerations

The SOIC-8 MMIC LNAs are fairly straightforward to use.

By following some basic design considerations, the

performance in the data sheet is easily achieved. The

following sections discuss the electrical (DC and RF),

manufacturing,

and

reliability

considerations

the

customer must keep in mind for proper use of these

MMIC LNAs.

Customer Electrical Considerations

These MMIC LNAs were designed to be used on low cost

FR4 printed circuit boards. Before discussing the proper

board layout, an understanding of each of the pins of the

LNA family is necessary. All the products of the MMIC

LNA family have the same pin assignments, shown

previously in Figure 7, except for the AM50-0002, which

will be discussed separately below. Pins 1, 4, 5, an 8 are

an optional bias control pin.

For nominal current

operation, no external connection is made to pin 2.

An important consideration is the off-chip components

passed with a 500-pF surface mount MLC capacitor

mounted as close as possible to the pin. RF decoupling

of the power supply with a chip inductor of at least 15 nH

is recommended. Pin 2 is a parallel connection to the first

stage FET source resistor and is normally left open.

Connecting a chip resistor from pin 2 to ground will

increase the current draw and extend the dynamic range

of the LNAs as shown on the data sheets and discussed

below in the product applications section. For the low

gain MAAM12022, MAAM12032, and MAAM22010,

connecting a 30-35 ohm resistor from pin 2 to ground will

increase the current 20 mA from nominal 5 mA. For the

high gain MAAM12021 and MAAM12031, connecting a

35-40 ohm resistor from pin 2 to ground will increase the

current to 20 mA from the nominal 8 mA. For the higher

current AM50-0001, a resistor ranging from 10-40 ohms

can be used. For each of these six LNAs, care must be

taken so the maximum current rating on the data sheet is

not exceeded.

The AM50-0002 has DC and RF ground pins everywhere

AM50-0002 requires a simple low loss external input

matching network. Figure 8 shows the functional diagram

of the AM50-0002 and details the requirements of the

matching network at 1.575 GHz.

output line, the bias can be coupled to the RF output line

using a simple bias tee network. Please note that the

AM50-0002 has no optional bias pin.

Sub

Lot

Operation

Condition

Qty.

Visual Inspection

General

500

Electrical Test

ATP at +25°C

500

Sub Lot Split

A

Electrical Test

ATP at -40,25,80°C

40

A

Infrared Reflow

Simulation

35 seconds above

235°C max 245°C

total of 180 seconds

392

A

Electrical Test

ATP at +25°C

392

Sub Lot Split

B

High Temperature

Operation Bias

150°C for 600 hrs

300

B

Electrical Test

ATP at 25°C

-40,25,80°C

280

20

C

Autoclave

96 hrs 100% RH 15

psi

76

C

Electrical Test

ATP at +25°C

76

D

Temperature Cycle

200 cycles -55 to

+150°C 30 min dwell

at extremes

96

D

Electrical

ATP at 25°C

-40,25,80°C

76

20

E

ESD Classification

MIL-STD-3015

6

F

DPA

REL-002

4

G

Physical Dimensions

100% of dimensions

coplanarity < 4 mils

22

G

Resistance to

Solvents

MIL-STD-2015

22

Table 1. One-time Product Qualification

Procedure