RL78 datasheet(71/100 Pages) RENESAS

71 / 100 page

RL78/G14

2. ELECTRICAL SPECIFICATIONS

R01DS0053EJ0100 Rev. 1.00

Page 71 of 97

Feb 21, 2012

Caution

The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.

Note 1.

Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps

Note 2.

Use it with EVDD0

 Vb.

Note 3.

The following conditions are required for low voltage interface when EVDD0 < VDD.

2.4 V

 EVDD0 < 2.7 V : MAX. 2.6 Mbps

1.8 V

 EVDD0 < 2.4 V : MAX. 1.3 Mbps

1.6 V

 EVDD0 < 1.8 V : MAX. 0.6 Mbps

Caution

Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD0 tolerance) mode for the TxDq

pin by using port input mode register g (PIMg) and port output mode register g (POMg).

Remark 1. Vb[V]: Communication line voltage

Remark 2.

q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)

Remark 3.

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00 to 03, 10 to 13)

Remark 4.

VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at

different potentials in UART mode.

4.0 V

 EVDD0  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V

2.7 V

 EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V

1.8 V

 EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V: VIH = 1.50 V, VIL = 0.32 V

Remark 5.

UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is

(6)

Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output)

(TA = -40 to +85

C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

(1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Transfer rate

Notes 1, 2

reception

4.0 V

 EVDD0  5.5 V,

2.7 V

 Vb  4.0 V

fMCK/6 Note 1

bps

Theoretical value of the

maximum transfer rate

fCLK = 32 MHz, fMCK = fCLK

5.3

Mbps

2.7 V

 EVDD0 < 4.0 V,

2.3 V

 Vb  2.7 V

fMCK/6 Note 1

bps

Theoretical value of the

maximum transfer rate

fCLK = 32 MHz, fMCK = fCLK

5.3

Mbps

1.8 V

 EVDD0 < 3.3 V,

1.6 V

 Vb  2.0 V

fMCK/6

Note 1 to Note 3

bps

Theoretical value of the

maximum transfer rate

fCLK = 8 MHz, fMCK = fCLK

1.3

Mbps

RL78 датащи(PDF) 71 Page - Renesas Technology Corp

RL78 датащи(HTML) 71 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

датащи скачать

ссылки URL