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05066.R7 9/10

Page 6

PSOT03LC - PSOT36LC

APPLICATION INFORmATION

FIGURE 1 - COmmON mODE I/O PORT PROTECTION

Two PSOTxxLC devices used in parallel. Circuit connectivity is as follows:

• I/O Line connected to Device 1, Pin 1.

• I/O Line connected to Device 2, Pin 2.

• Device 1, Pin 2 connected to ground.

• Device 2, Pin 1 connected to ground.

• Device 1 and 2, Pin 3 not connected.

CIRCUIT BOARD RECOmmENDATIONS

Circuit board layout is critical for electromagnetic compatibility protection. The following guidelines are recommended:

• The protection device should be placed near the input terminals or connectors, the device will divert the transient current

immediately before it can be coupled into the nearby traces.

• The path length between the TVS device and the protected line should be minimized.

• All conductive loops including power and ground loops should be minimized.

• The transient current return path to ground should be kept as short as possible to reduce parasitic inductance.

• Ground planes should be used whenever possible. For multilayer PCBs, use dedicated ground planes

2

3

1

2

3

1

I/O LINE

GND

2

3

1

2

3

1

I/O 1

I/O 2

FIGURE 1 - DIFFERENTIAL mODE EThERNET PROTECTION

Two PSOTxxLC devices used in parallel. Circuit connectivity is as follows:

• I/O Line 1 connected to Device 1, Pin 1.

• I/O Line 1 connected to Device 2, Pin 2.

• I/O Line 2 connected to Device 1, Pin 1.

• I/O Line 2 connected to Device 2, Pin 2.

• Device 1 and 2, Pin 3 not connected.