ANALOG PRODUCTS DIVISION

561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715

www.protekanalog.com

PA5331

Low Power 24-Bit, Stereo Audio CODEC

With Headphone Amplifier

95250 Rev.0. 01/10

NOT FOR USE IN LIFE SUPPORT SYSTEMS

CHIP CONTROL AND POWER MANAGEMENT

Register 0

– Chip Control 1, Default 0000 0110

Bit Name

Bit

Description

SCPReset

7

0

– normal (default)

1

– reset control port register to default

LRCM

6

0

– ALRCK disabled when both ADC disabled; DLRCK disabled when both DAC disabled (default)

1

– ALRCK and DLRCK disabled when all ADC and DAC disabled

DACMCLK

5

0

– when SameFs=1, ADCMCLK is the chip master clock source (default)

1

– when SameFs=1, DACMCLK is the chip master clock source

SameFs

4

0

– ADC Fs differs from DAC Fs (default)

1

– ADC Fs is the same as DAC Fs

SeqEn

3

0

– internal power up/down sequence disable (default)

1

– internal power up/down sequence enable

EnRef

2

0

– disable reference

1

– enable reference (default)

VMIDSEL

1:0

00

– Vmid disabled

01

– 50 k divider enabled

10

– 500 k divider enabled (default)

11

– 5 k divider enabled

Register 1

– Chip Control 2, Default 0001 1100

Bit Name

Bit

Description

TSDEN

7

0

– thermal shutdown disabled (default)

1

– thermal shutdown enabled

PdnOC

6

0

– over current shutdown disabled (default)

1

– over current shutdown enabled

LPVcmMod

5

0

– normal (default)

1

– low power

LPVrefBuf

4

0

– normal

1

– low power (default)

PdnAna

3

0

– normal

1

– entire analog power down (default)

PdnIbiasgen

2

0

– normal

1

– ibiasgen power down (default)

VrefLo

1

0

– normal (default)

1

– low power

PdnVrefbuf

0

0

– normal (default)

1

– power down

Register 2

– Chip Power Management, Default 1100 0011

Bit Name

Bit

Description

adc_DigPDN

7

0

– normal

1

– resets ADC DEM, filter and serial data port (default)

dac_DigPDN

6

0

– normal

1

– resets DAC DSM, DEM, filter and serial data port (default)

adc_stm_rst

5

0

– normal (default)

1

– reset ADC state machine to power down state

dac_stm_rst

4

0

– normal (default)

1

– reset DAC state machine to power down state

ADCDLL_PDN

3

0

– normal (default)

1

– ADC_DLL power down, stop ADC clock

DACDLL_PDN

2

0

– normal (default)

1

– DAC DLL power down, stop DAC clock

adcVref_PDN

1

0

– ADC analog reference power up

1

– ADC analog reference power down (default)

dacVref_PDN

0

0

– DAC analog reference power up

1

– DAC analog reference power down (default)